From patchwork Thu Nov 3 12:51:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Vesker X-Patchwork-Id: 119431 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C4902A00C2; Thu, 3 Nov 2022 13:52:15 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B924A42685; Thu, 3 Nov 2022 13:52:15 +0100 (CET) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2059.outbound.protection.outlook.com [40.107.244.59]) by mails.dpdk.org (Postfix) with ESMTP id 6324D40F19 for ; Thu, 3 Nov 2022 13:52:14 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VkQIximDHtLBRbvHukrnTXFnhveVvsTQ3yBbZzqSleNesDmVY2Ov/Pn5Jmsy0BXpJ8rnaA9uGdkjXklGmdH/fXK982M6/Dxl6bQxB72CvCOkVKH4HcIubn7wtI0LtENWucGMH/2loIhANLUbeWlKCXMHGfIUK4zX8L/Hi/UNMzMNMCwQBJ8UP4m4Gcyr2u0hTobgTDfdQXscidzp4hmpYjlT2vXffi957xfg3yQrzaVIi7G7/fY3yPwQOfrdYqnS6BYIBgkjS5z01JFiIM5LLPGfphkWjEqbjRm8L7MsxeXxlcvsPHUMDOaYMiv3AV+L6mENNcAxTHQfO3oc/4AfxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9A21PeT8Ky1D996eBeGmodpdW9Gv1GX9mKXoJtzphHc=; b=TnZiwaN8NH9NCKV6JK3qaCyZ3lX5IXi5AoZQSB9Yqk5eo4m5W8NNpyCEAqNvqYa3Ff+iLBNn/VrujzmDR71lsTGtl+Cdo02FMSMT+YR8szjNBOVleBUhHsjVQ9zeKskaMjueDNlwrwakRN81gpm6MCX+72bITQNabY6aBcwc7VZRm90crC6J80TL8ITnz+jxnF+TCnbG+V+ytCEew6v5rYUX1ce1yMc6BNNxjjjY0mUD5HXrb8zsyAs0qECvoDXPx0OAr9uStyum4dliK53W3tD5IAQHuvtWofDMExchXHNeLpsEzcbB6Cc/HHkiED8Tsk/DsarKrdRjRp2d/BEWKw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9A21PeT8Ky1D996eBeGmodpdW9Gv1GX9mKXoJtzphHc=; b=PmGLTZjb32a3/LM63WfYhltBiaS/ZICNi6zDirH1pCRsug/rJqBbTBfLMvE3ZNKthqkV1ZO29S2ReS3sGhKCmMqIFoBxI2Hk2Cfo5nib6LWsmVA4RCs9s1OqhZm0UgKavNZY3J1mQTJKHVO1x5kOm4VptJmI1WSHUopBx6pvLaeoPgsCQhUY9zbsHcKSuFdxIw9GiCNfZgJxchySWkzZiV92GstniDeZIbLDNp6mYglryFhno6VERFWWu6Iyd3KY1K1LWkd1bi6hCq5iKJfJqJZShcmRKMk9hB7+pjpX3uRokSuT4R+oMRPI0dh5SGgeMZ1CP0QU0z8m8wGyXMhxFQ== Received: from MW4PR04CA0058.namprd04.prod.outlook.com (2603:10b6:303:6a::33) by DM4PR12MB5216.namprd12.prod.outlook.com (2603:10b6:5:398::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.19; Thu, 3 Nov 2022 12:52:12 +0000 Received: from CO1NAM11FT026.eop-nam11.prod.protection.outlook.com (2603:10b6:303:6a:cafe::c9) by MW4PR04CA0058.outlook.office365.com (2603:10b6:303:6a::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.22 via Frontend Transport; Thu, 3 Nov 2022 12:52:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CO1NAM11FT026.mail.protection.outlook.com (10.13.175.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.20 via Frontend Transport; Thu, 3 Nov 2022 12:52:10 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 3 Nov 2022 05:52:02 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 3 Nov 2022 05:52:00 -0700 From: Alex Vesker To: , , , , Matan Azrad CC: , Subject: [PATCH] net/mlx5/hws: fix possible negative return on sq create Date: Thu, 3 Nov 2022 14:51:46 +0200 Message-ID: <20221103125146.7291-1-valex@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT026:EE_|DM4PR12MB5216:EE_ X-MS-Office365-Filtering-Correlation-Id: ead7d28d-2f89-409b-e5b4-08dabd9a38dc X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DKLbBU52b8650MWLm9L+jwKCpO19sANavgfbXDGG9KSGsFHWU0yzlqjamhclio47YX9uABM91hG9GNENh5SHCB53/cfK/72fY6YADtdXjm0lt9n9BZBB1qXEZVpEozm8/we+oJZc5bF3jcSojABxtGEO6I+3JKUfb8xR2e6vTcxIgBGKqjvNWfz7Nis1cxrrMwk5m0ISE1GQf5SIpjmMKKxFEionjNwGYiUMzThh+w/2Qjc7Baxg8WCLPqqI8P/9US+L3Lue52gaQDdJGhWJSdC2c7nj8Ir5Co75lo86K5OcJaaiYB0I88750AC5nOF2RW0q+4HxoHS0GSU2l6oGbj5KDAkxCDA/8/mqhDu8t/SXYKKze5KUICGDMBQFLOLQZfcOXC+0JQ6kl3C2mDKyCzyu8Ca0VJmpiBrTAqAF4mrd/YRR2aqadP4IHPElhgWsL2+93LYmYlXXA8DtGbPFE9b1BNDkLTkj77V6+dCCaElmdr9sPTokF0MdcdzRKk1pEGbfCV4uF3OL/C2KeK0X0+ywkKfyHKEBg71LS14zXGcEijLxbvQ9hY8ixp7OrNN2FonkXSuIIV6cmwT3dvGa8PxR1EXlzmlMzaAbgOmcPHgsdlYF5a8iy0HNinOCt0z0eAPNV9zVq5jzscalK4YheYBdiNpTtQvuXJYMN9ffeasDQ+1KS5B7U5yqER7skel3yQPATILM85U0QduZZt0kgBH8yULSxqdlrfk4CSiA8Ktg0pkWhzbrTgfXG/FhDDbzQP+ZZZlAxNvixRdr3nk98w== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(396003)(346002)(376002)(136003)(451199015)(46966006)(36840700001)(40470700004)(478600001)(6636002)(54906003)(7696005)(316002)(107886003)(26005)(2616005)(110136005)(36756003)(6286002)(4326008)(40460700003)(82310400005)(40480700001)(55016003)(41300700001)(8936002)(8676002)(6666004)(426003)(5660300002)(82740400003)(7636003)(36860700001)(356005)(86362001)(2906002)(70586007)(336012)(70206006)(83380400001)(186003)(47076005)(1076003)(16526019); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2022 12:52:10.2023 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ead7d28d-2f89-409b-e5b4-08dabd9a38dc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5216 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The sysconf call can return a negative value (-1) on failure this will lead to posix_memalign to fail. This is not a realistic case which was found by the static checkers. Fixes: 3eb7488 ("net/mlx5/hws: add send layer") Signed-off-by: Alex Vesker Reviewed-by: Erez Shitrit --- drivers/net/mlx5/hws/mlx5dr_send.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_send.c b/drivers/net/mlx5/hws/mlx5dr_send.c index 26904a9040..1e9953a38f 100644 --- a/drivers/net/mlx5/hws/mlx5dr_send.c +++ b/drivers/net/mlx5/hws/mlx5dr_send.c @@ -524,6 +524,7 @@ static int mlx5dr_send_ring_open_sq(struct mlx5dr_context *ctx, size_t sq_log_buf_sz; size_t buf_aligned; size_t sq_buf_sz; + size_t page_size; size_t buf_sz; int err; @@ -532,8 +533,9 @@ static int mlx5dr_send_ring_open_sq(struct mlx5dr_context *ctx, sq_buf_sz = 1 << (sq_log_buf_sz + log2above(MLX5_SEND_WQE_BB)); sq->reg_addr = queue->uar->reg_addr; - buf_aligned = align(sq_buf_sz, sysconf(_SC_PAGESIZE)); - err = posix_memalign((void **)&sq->buf, sysconf(_SC_PAGESIZE), buf_aligned); + page_size = sysconf(_SC_PAGESIZE); + buf_aligned = align(sq_buf_sz, page_size); + err = posix_memalign((void **)&sq->buf, page_size, buf_aligned); if (err) { rte_errno = ENOMEM; return err;