From patchwork Tue Oct 18 19:41:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 118475 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 30C7AA0560; Tue, 18 Oct 2022 21:43:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2566240A8B; Tue, 18 Oct 2022 21:43:42 +0200 (CEST) Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2056.outbound.protection.outlook.com [40.107.212.56]) by mails.dpdk.org (Postfix) with ESMTP id 448A542670 for ; Tue, 18 Oct 2022 21:43:40 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HxVLDWC3XBUCxKxggSELXJdOWLAenyhpZ9nnapEIR4drW5egFooWZHzWIU4FsUhI7hbd1T/AJGwOPXbY13L/5c4JO/ioWE938WN23uQBpNpafz+DVRRnGhyEiIy4Oj5cqO40RxykKvbVJ0BSCDAtoYwVH1D3vmwdcPGgvC8d9G2XKeO7265LNdgKPv3Vq/8Z+44qWGCwhHh6pHk71zXsfWfT8daGfX8PlKNRB1kHcHLJr6UYaEjNe2uUsCcqyYeZqTP7EW64nzDRTyfC0+1scyn7/XjUBz8xBtSKtf6loo8YurLCFXA3cm//Ub9fmpv+KOosYQff29kdZL7crfsYVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WCKmUGVCap2foJU9K803lLjoIApCRHGwBTUBZCRZjGo=; b=dLOhRrmCwjpPfPu/sFCuC1w4G+/fbv1s7Tiy5K6uIxokPxabk7UM4QV4bIkOmoxeaJbGypV2GaRrml3MY4NI4SXH1j/UV4aomSJBi69sZHINsmnGGjoMFSGCIxNlqYZ862AbWMj1Msc05zMHcMbfMgKFhly9lBSQ4kHtIyy+8ATkzIZLZw415SvpA7dIS25CzG9kazAXmVn5TAUPupL5aKjMvnCUVDgos5Ly6/akTHiD9gBWTl+k8IHyL/JRykuGjMEZQXjPOYEbb2Undhw4JJBCe7MIWl9bRxZSl85tiJ//HejYtIvB7STW5LPkh/dL4DRdfkiLrvJReyWITPrviw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=dpdk.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WCKmUGVCap2foJU9K803lLjoIApCRHGwBTUBZCRZjGo=; b=VepdCMNJuOl6FrXVpLMZ98yfJN6//xWpoXEfr2cWGelDVX4nVXYSfMigHTLidra/dpwihcmdUdS0xXmmYhC3PeT0WsuRE8b0bSUHiAxL4TGxGyqdKm5CwfpO0yWudHvRF0N/kpdffTFOMtbCtmLz9+o8S80PuHTqrOafb2VT5GE= Received: from BN9PR03CA0335.namprd03.prod.outlook.com (2603:10b6:408:f6::10) by IA1PR12MB6068.namprd12.prod.outlook.com (2603:10b6:208:3ec::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.33; Tue, 18 Oct 2022 19:43:38 +0000 Received: from BN8NAM11FT054.eop-nam11.prod.protection.outlook.com (2603:10b6:408:f6:cafe::4c) by BN9PR03CA0335.outlook.office365.com (2603:10b6:408:f6::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.34 via Frontend Transport; Tue, 18 Oct 2022 19:43:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT054.mail.protection.outlook.com (10.13.177.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5746.16 via Frontend Transport; Tue, 18 Oct 2022 19:43:38 +0000 Received: from driver-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 18 Oct 2022 14:43:34 -0500 From: Andrew Boyer To: CC: Andrew Boyer , R Mohamed Shah Subject: [PATCH v2 09/36] net/ionic: update MTU calculations Date: Tue, 18 Oct 2022 12:41:04 -0700 Message-ID: <20221018194131.23006-10-andrew.boyer@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011005032.47584-1-andrew.boyer@amd.com> References: <20221011005032.47584-1-andrew.boyer@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT054:EE_|IA1PR12MB6068:EE_ X-MS-Office365-Filtering-Correlation-Id: b68bf19f-6d86-4189-5c6c-08dab1410d54 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NwiXBatTBkQvvBEj5moJ1TAXf0GAvVJjDYsjqQs/4vmzskv8LzMJb3Sb9v8uQ+gYTvs2GysI3quHg6ddWRe5OBpXANOCb1Xz3XzY+R0vlpnnUw61DJwEFHiXaOMHSIIiqqBNM7Ik9Vt2/xsa/cZt5lrHMPqy7QPT315v2fqmFn6bICQ9uW8DrF0F33+ubYYGjDKfzQmnXoUM22bygQa5fT/ajx+jJCZE71sHCmel1MlwRIjYuX6csY90pj44QXzL5emBccm7tN8MHg9H//gYGR7I/bf/V6ZMOKVw8ut0OnKcEgFLHSKNMbVK7OswgFVJXaNfiRhy0pRFQy7SaLiMv90NQtCW/7n5ERvavdsHpGhk/BcNR5Ra/07nQQ4wvqJU6StJHTmpkrBNwliYa7qKBOBBg35cmoXpNyEdjJFp5fP6Ob8BiujKAaUsoaNdHYEIBBuw4q6anZNksio3JT00lWJF+cdTYHc0Yvb18PwP/MY2n4jVZ5txBMZ/+Jg1zN+MbaSjRN4T+qUgjQv+0IbCym5B1Sweuwb0VfdlRaiRRGir69PYS33n7NjER5B/WTMQwUZKK8lAwJ50QvqPilQtyVRFf3GgVGVNcNRpKE0Hk6UMP05Zp/+N1+1wPh8p4leA8QE9vyqJMlTTFvcpanPBfns3AntX+vUhyoOhuFVpyoyohJujUFBXBQsa6jQTw+txSn6IrKLlLHS28qyycptQPWhD4Y9ATFL8askJeUTPytPQMxMHSRil7ujfAZLz/WwxmmdLKru78wu0g5MeHkGaJKzc7wJLxJ6BdqK0eS038wfyg2gCVcH34SlbE7foqdbv X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(396003)(39860400002)(376002)(136003)(346002)(451199015)(40470700004)(36840700001)(46966006)(1076003)(186003)(2616005)(26005)(36860700001)(336012)(6666004)(426003)(47076005)(83380400001)(2906002)(5660300002)(16526019)(44832011)(40480700001)(15650500001)(40460700003)(6916009)(54906003)(316002)(41300700001)(8936002)(4326008)(8676002)(70206006)(70586007)(82310400005)(478600001)(86362001)(36756003)(356005)(81166007)(82740400003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2022 19:43:38.0657 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b68bf19f-6d86-4189-5c6c-08dab1410d54 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6068 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Test min and max MTU against values read from firmware, for correctness. Update the firmware field name, for clarity. The device must be stopped before changing MTU, for correctness. Store the calculated frame size in the queue, for performance. Signed-off-by: Andrew Boyer Signed-off-by: R Mohamed Shah --- drivers/net/ionic/ionic_dev.h | 5 +++- drivers/net/ionic/ionic_ethdev.c | 40 +++++++++++++++++++++----------- drivers/net/ionic/ionic_if.h | 8 +++---- drivers/net/ionic/ionic_lif.c | 10 +++----- drivers/net/ionic/ionic_lif.h | 4 +++- drivers/net/ionic/ionic_rxtx.c | 26 +++++++++------------ 6 files changed, 51 insertions(+), 42 deletions(-) diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h index fabc21834a..7aea9c9907 100644 --- a/drivers/net/ionic/ionic_dev.h +++ b/drivers/net/ionic/ionic_dev.h @@ -11,8 +11,11 @@ #include "ionic_if.h" #include "ionic_regs.h" +#define VLAN_TAG_SIZE 4 + #define IONIC_MIN_MTU RTE_ETHER_MIN_MTU -#define IONIC_MAX_MTU 9194 +#define IONIC_MAX_MTU 9378 +#define IONIC_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE) #define IONIC_MAX_RING_DESC 32768 #define IONIC_MIN_RING_DESC 16 diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c index 2b7c05a9f2..637553716d 100644 --- a/drivers/net/ionic/ionic_ethdev.c +++ b/drivers/net/ionic/ionic_ethdev.c @@ -343,18 +343,17 @@ static int ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) { struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); - int err; - IONIC_PRINT_CALL(); + if (lif->state & IONIC_LIF_F_UP) { + IONIC_PRINT(ERR, "Stop %s before setting mtu", lif->name); + return -EBUSY; + } - /* - * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU - * is done by the API. - */ + /* Note: mtu check against min/max is done by the API */ + IONIC_PRINT(INFO, "Setting mtu %u", mtu); - err = ionic_lif_change_mtu(lif, mtu); - if (err) - return err; + /* Update the frame size used by the Rx path */ + lif->frame_size = mtu + IONIC_ETH_OVERHEAD; return 0; } @@ -376,12 +375,16 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev, rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ - dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; - dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; - dev_info->max_mac_addrs = adapter->max_mac_addrs; - dev_info->min_mtu = IONIC_MIN_MTU; - dev_info->max_mtu = IONIC_MAX_MTU; + dev_info->min_mtu = RTE_MAX((uint32_t)IONIC_MIN_MTU, + rte_le_to_cpu_32(ident->lif.eth.min_mtu)); + dev_info->max_mtu = RTE_MIN((uint32_t)IONIC_MAX_MTU, + rte_le_to_cpu_32(ident->lif.eth.max_mtu)); + dev_info->min_rx_bufsize = dev_info->min_mtu + IONIC_ETH_OVERHEAD; + dev_info->max_rx_pktlen = dev_info->max_mtu + IONIC_ETH_OVERHEAD; + dev_info->max_lro_pkt_size = + eth_dev->data->dev_conf.rxmode.max_lro_pkt_size; + dev_info->max_mac_addrs = adapter->max_mac_addrs; dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; dev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; @@ -889,6 +892,15 @@ ionic_dev_start(struct rte_eth_dev *eth_dev) if (dev_conf->lpbk_mode) IONIC_PRINT(WARNING, "Loopback mode not supported"); + lif->frame_size = eth_dev->data->mtu + IONIC_ETH_OVERHEAD; + + err = ionic_lif_change_mtu(lif, eth_dev->data->mtu); + if (err) { + IONIC_PRINT(ERR, "Cannot set LIF frame size %u: %d", + lif->frame_size, err); + return err; + } + err = ionic_lif_start(lif); if (err) { IONIC_PRINT(ERR, "Cannot start LIF: %d", err); diff --git a/drivers/net/ionic/ionic_if.h b/drivers/net/ionic/ionic_if.h index c9c4a9dee4..79aa196345 100644 --- a/drivers/net/ionic/ionic_if.h +++ b/drivers/net/ionic/ionic_if.h @@ -401,8 +401,8 @@ union ionic_lif_config { * @version: Ethernet identify structure version * @max_ucast_filters: Number of perfect unicast addresses supported * @max_mcast_filters: Number of perfect multicast addresses supported - * @min_frame_size: Minimum size of frames to be sent - * @max_frame_size: Maximum size of frames to be sent + * @min_mtu: Minimum MTU of frames to be sent + * @max_mtu: Maximum MTU of frames to be sent * @config: LIF config struct with features, mtu, mac, q counts * * @rdma: RDMA identify structure @@ -434,8 +434,8 @@ union ionic_lif_identity { __le32 max_ucast_filters; __le32 max_mcast_filters; __le16 rss_ind_tbl_sz; - __le32 min_frame_size; - __le32 max_frame_size; + __le32 min_mtu; + __le32 max_mtu; u8 rsvd2[106]; union ionic_lif_config config; } __rte_packed eth; diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index 0d167f677f..13c763407c 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -536,7 +536,7 @@ ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) } int -ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu) +ionic_lif_change_mtu(struct ionic_lif *lif, uint32_t new_mtu) { struct ionic_admin_ctx ctx = { .pending_work = true, @@ -546,13 +546,8 @@ ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu) .mtu = rte_cpu_to_le_32(new_mtu), }, }; - int err; - - err = ionic_adminq_post_wait(lif, &ctx); - if (err) - return err; - return 0; + return ionic_adminq_post_wait(lif, &ctx); } int @@ -730,6 +725,7 @@ ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index, int err; flags = IONIC_QCQ_F_SG; + err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, sizeof(struct ionic_rx_qcq), diff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h index b37841b69f..c87f981803 100644 --- a/drivers/net/ionic/ionic_lif.h +++ b/drivers/net/ionic/ionic_lif.h @@ -81,6 +81,7 @@ struct ionic_rx_qcq { /* cacheline2 */ struct rte_mempool *mb_pool; + uint16_t frame_size; /* Based on configured MTU */ uint16_t flags; /* cacheline3 (inside stats) */ @@ -123,6 +124,7 @@ struct ionic_lif { struct ionic_adapter *adapter; struct rte_eth_dev *eth_dev; uint16_t port_id; /**< Device port identifier */ + uint16_t frame_size; uint32_t hw_index; uint32_t state; uint32_t ntxqcqs; @@ -181,7 +183,7 @@ int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr); int ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb, void *cb_arg); -int ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu); +int ionic_lif_change_mtu(struct ionic_lif *lif, uint32_t new_mtu); int ionic_dev_add_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr, diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index ffca26dd3e..ce1bdbc2c3 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -772,8 +772,6 @@ ionic_rx_clean(struct ionic_rx_qcq *rxq, struct ionic_rxq_comp *cq_desc_base = cq->base; struct ionic_rxq_comp *cq_desc = &cq_desc_base[cq_desc_index]; struct rte_mbuf *rxm, *rxm_seg; - uint32_t max_frame_size = - rxq->qcq.lif->eth_dev->data->mtu + RTE_ETHER_HDR_LEN; uint64_t pkt_flags = 0; uint32_t pkt_type; struct ionic_rx_stats *stats = &rxq->stats; @@ -814,8 +812,7 @@ ionic_rx_clean(struct ionic_rx_qcq *rxq, return; } - if (cq_desc->len > max_frame_size || - cq_desc->len == 0) { + if (cq_desc->len > rxq->frame_size || cq_desc->len == 0) { stats->bad_len++; ionic_rx_recycle(q, q_desc_index, rxm); return; @@ -936,7 +933,7 @@ ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index, } static __rte_always_inline int -ionic_rx_fill(struct ionic_rx_qcq *rxq, uint32_t len) +ionic_rx_fill(struct ionic_rx_qcq *rxq) { struct ionic_queue *q = &rxq->qcq.q; struct ionic_rxq_desc *desc, *desc_base = q->base; @@ -961,7 +958,7 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq, uint32_t len) info = IONIC_INFO_PTR(q, q->head_idx); - nsegs = (len + buf_size - 1) / buf_size; + nsegs = (rxq->frame_size + buf_size - 1) / buf_size; desc = &desc_base[q->head_idx]; dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(rxm)); @@ -996,9 +993,9 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq, uint32_t len) prev_rxm_seg = rxm_seg; } - if (size < len) + if (size < rxq->frame_size) IONIC_PRINT(ERR, "Rx SG size is not sufficient (%d < %d)", - size, len); + size, rxq->frame_size); info[0] = rxm; @@ -1016,7 +1013,6 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq, uint32_t len) int __rte_cold ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) { - uint32_t frame_size = eth_dev->data->mtu + RTE_ETHER_HDR_LEN; uint8_t *rx_queue_state = eth_dev->data->rx_queue_state; struct ionic_rx_qcq *rxq; int err; @@ -1029,8 +1025,10 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) rxq = eth_dev->data->rx_queues[rx_queue_id]; - IONIC_PRINT(DEBUG, "Starting RX queue %u, %u descs (size: %u)", - rx_queue_id, rxq->qcq.q.num_descs, frame_size); + rxq->frame_size = rxq->qcq.lif->frame_size - RTE_ETHER_CRC_LEN; + + IONIC_PRINT(DEBUG, "Starting RX queue %u, %u descs, size %u", + rx_queue_id, rxq->qcq.q.num_descs, rxq->frame_size); if (!(rxq->flags & IONIC_QCQ_F_INITED)) { err = ionic_lif_rxq_init(rxq); @@ -1041,7 +1039,7 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) } /* Allocate buffers for descriptor rings */ - if (ionic_rx_fill(rxq, frame_size) != 0) { + if (ionic_rx_fill(rxq) != 0) { IONIC_PRINT(ERR, "Could not alloc mbuf for queue:%d", rx_queue_id); return -1; @@ -1129,8 +1127,6 @@ ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) { struct ionic_rx_qcq *rxq = rx_queue; - uint32_t frame_size = - rxq->qcq.lif->eth_dev->data->mtu + RTE_ETHER_HDR_LEN; struct ionic_rx_service service_cb_arg; service_cb_arg.rx_pkts = rx_pkts; @@ -1139,7 +1135,7 @@ ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, ionic_rxq_service(rxq, nb_pkts, &service_cb_arg); - ionic_rx_fill(rxq, frame_size); + ionic_rx_fill(rxq); return service_cb_arg.nb_rx; }