From patchwork Mon Oct 17 16:00:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, YuanX" X-Patchwork-Id: 118256 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A2A5A0556; Mon, 17 Oct 2022 10:16:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7BC784021D; Mon, 17 Oct 2022 10:16:26 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 7E80541181 for ; Mon, 17 Oct 2022 10:16:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665994585; x=1697530585; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=gjA0k2FIDLVCh9K7IoB341qSBHxFfI56LwOe9PmByKA=; b=XCjZsLZ55vCDtm4dCmI9hnpsthwMXg7a22c+8C6yXrb4KTP/xkg8KxzC vADWrRw9OiICbuvpd8mX3uGYeB/DmjVeJKEE3iiNhMoO5S7oHUvwGZ5RQ y/w7Ii+m5XaTsxbLgWcuR2dxWbadSK8X7beYu+2sVboK22UtvlDqEc5XM Xql+XlPs0iDQOUJaJlIy8C0Ma8mRvXrIEoVzmQrWy6uRro1nv4adyJtxU dxvZw8QjNuAJqDhEsBO+yiSQS/xkR3VcGJj1FQLEqtpUS2O7IV0eOEj5m nHiBB0w3tlYCs2tPIonII0ZI7iptEfMBG4XyrFY3EnpxyQAwrjv70a0N4 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="303353450" X-IronPort-AV: E=Sophos;i="5.95,191,1661842800"; d="scan'208";a="303353450" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 01:16:24 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="753553565" X-IronPort-AV: E=Sophos;i="5.95,191,1661842800"; d="scan'208";a="753553565" Received: from unknown (HELO localhost.localdomain) ([10.239.252.55]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 01:16:22 -0700 From: Yuan Wang To: Qiming Yang , Qi Zhang Cc: dev@dpdk.org, xuan.ding@intel.com, yaqi.tang@intel.com, Yuan Wang Subject: [PATCH] net/ice: fix the judgment order of buffer split Date: Tue, 18 Oct 2022 00:00:21 +0800 Message-Id: <20221017160021.773879-1-yuanx.wang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org proto_hdr defines a bit mask of the protocol sequence as RTE_PTYPE_*, The last RTE_PTYPE* in the mask indicates the split position. To get the split position from hdr_proto, the order of judgement should be from inner to outer layer, so for tunneling packets the tunnel header should be placed at the end of the judgement condition. Fixes: 629dad3ef325 ("net/ice: support buffer split in scalar Rx") Signed-off-by: Yuan Wang --- drivers/net/ice/ice_rxtx.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index 953ff217df..7a2d5829c0 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -324,13 +324,6 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq) goto set_hsplit_finish; } - switch (proto_hdr & RTE_PTYPE_TUNNEL_MASK) { - case RTE_PTYPE_TUNNEL_GRENAT: - rx_ctx.dtype = ICE_RX_DTYPE_HEADER_SPLIT; - rx_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS; - goto set_hsplit_finish; - } - switch (proto_hdr & RTE_PTYPE_INNER_L4_MASK) { case RTE_PTYPE_INNER_L4_TCP: case RTE_PTYPE_INNER_L4_UDP: @@ -358,6 +351,13 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq) goto set_hsplit_finish; } + switch (proto_hdr & RTE_PTYPE_TUNNEL_MASK) { + case RTE_PTYPE_TUNNEL_GRENAT: + rx_ctx.dtype = ICE_RX_DTYPE_HEADER_SPLIT; + rx_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS; + goto set_hsplit_finish; + } + PMD_DRV_LOG(ERR, "Buffer split protocol is not supported"); return -EINVAL;