From patchwork Fri Oct 14 11:48:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Vesker X-Patchwork-Id: 118214 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ECC9AA00C2; Fri, 14 Oct 2022 13:51:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F235142DF3; Fri, 14 Oct 2022 13:49:48 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2045.outbound.protection.outlook.com [40.107.223.45]) by mails.dpdk.org (Postfix) with ESMTP id 8914942E03 for ; Fri, 14 Oct 2022 13:49:47 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=cTweZfP6tTpRGfhllQQq/U6clRTbiIrscL4/ej0dpzmOkNmHsDrGiFYuG8LLZK0iOdkuLON2z3lfOfg9C2EuxeDRsrtLz2mqSHz+HaktC53nEsao1yWq8JjFYKbn1uVhapIarTJlP4k3eB/Itr1Ob4IrQaOfDj5qkz6lknAqOzickp5O9eI2Zay05TwidNXONVw79E79o4plBtutPFUEEwLYnMYJstTYABqGff8OL0bcVHSIR15Pojo71U2aHuj/HFYIEMAo7bN4nBWePsmBYY0Hoj2cbZogKjmDnTDU0OchkpCtgHy7MJbeJ1eALWz/X0C8DeF+Kv77IlPi1PVEzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=LB6Dd8jDR97FcOAdD1772udo4FwYMHPq20KW/o5z2Xs=; b=BT2IeO9sOsFXxDLIqR6zIJMvjYYk+RIYNJQTC3FUA1goaYjm8x7F40VHfzBN/TZWJREeLMhpdF3dLaPqGFV82GcjZVBC08a8HuxuhCBVFwIOleNDFSt+AhN0Fz4Hg0ZsVGPOC/B9yQ7n8i5qx0Ct9sEv0TSv3XekQ5hu5ENJfYZf14Xu4Ok89DoJxib0e+vKqR/hEJoSs6LBTGqsw+QalVyY1nXDbjMiEZmM2EEtBakIRzedpILEOAGDXY4MEzHj6+8Eek9+wi+lvCEQZ4/kuqQKpNR2S4sCWow88ZOBBcfmdY5vRLiemm7mvFXvJY17W1pOicxq8y2pKS9WmHJfiA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LB6Dd8jDR97FcOAdD1772udo4FwYMHPq20KW/o5z2Xs=; b=Oy18kWWJdoEQC7UyN3Bi507b60uoC26ZBjZLTGZ6++bBL2u0fVxIW6TXGUw97tTJAx8VPqfAIS+pojkUbtWAITADn/439mdxE38Y9hpsnW6RaVuegUHWEI1ejJxEmo19n0IRy/6i/Bf3uLijEWS0NAzNvaD1Wmh3vUc6M6tF+cQIGO1V2URGZeecobCxR4ChY9E1mOvVzpujQ7HTllaDO40k8zRRkKzeYA84ed40lco8bwXCMpCWGNK7+nt1uG/kdpOvRr+GzqEn0EE+bx9771dk4qVhzZdI5SlpQocELR/Q/KjKKEor5Zf6I1ymYxCRwWiiXoP0HIvVXpOHro2a7A== Received: from MW4PR02CA0021.namprd02.prod.outlook.com (2603:10b6:303:16d::31) by LV2PR12MB5824.namprd12.prod.outlook.com (2603:10b6:408:176::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.22; Fri, 14 Oct 2022 11:49:45 +0000 Received: from CO1NAM11FT071.eop-nam11.prod.protection.outlook.com (2603:10b6:303:16d:cafe::f0) by MW4PR02CA0021.outlook.office365.com (2603:10b6:303:16d::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.22 via Frontend Transport; Fri, 14 Oct 2022 11:49:44 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1NAM11FT071.mail.protection.outlook.com (10.13.175.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.20 via Frontend Transport; Fri, 14 Oct 2022 11:49:44 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 14 Oct 2022 04:49:35 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 14 Oct 2022 04:49:32 -0700 From: Alex Vesker To: , , , , Matan Azrad CC: , , Erez Shitrit Subject: [v3 13/18] net/mlx5/hws: Add HWS table object Date: Fri, 14 Oct 2022 14:48:28 +0300 Message-ID: <20221014114833.13389-14-valex@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221014114833.13389-1-valex@nvidia.com> References: <20220922190345.394-1-valex@nvidia.com> <20221014114833.13389-1-valex@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT071:EE_|LV2PR12MB5824:EE_ X-MS-Office365-Filtering-Correlation-Id: da507ad4-c56c-4b06-80ca-08daadda2fe8 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: e15RqUkbg+U0uq2Hj2UHFNRW0JidbCeLYKTrzZonVXCZduXintj6rsNtE1bMGdRmEvUbmCImmo60cMNLQBIz+xrObusCXXelpSR02kkCdkKIQ8fz31izwT2jiMKo/Xde3twEzeCufrWalAYqSNvKtq8ickAZBA/BHZYUF9BmYqaHdJBn1Wns6WJ/z/RtPxZKQLQik/lER5u6uvT9AAfwJ3MTuMp2lUCFuElu8MFQaYsAmpNdzpxbarLkI4oqBAZU1txGtKsu+4FoYdrpYojTyy6AYay6YxnMsfd8nrMbpm9NaSUzABywHGuSYrznIBIblhe88870wDp4C4W7oylBOn5rvufFDIOpQ7O7KA3D21SjoVe1b7P5ojbi07rQixkT6cp94jniT1EmpW1wqoUd1WULbcCaEmhCD5+dXO4EpxqY8+V4vC6X5kGpl355EtxGyWJpqYSKhPmTBHnEaqht3iBXWobSazXDUJLrTyUf+nGxePsTWozIIBg8RZNOq1x4KOHq/xU76dZcTFgLfZvBP3xbsClne+AJ3Ps3YPt8K2hXrCqoyWfSMfMZ4v2oE88i/BqCawSG8PN5+IQ7NeiM7qTYV8OvPHPip3ESA3S8BEamPJRSNouazZt6bK6g5niwYx+iNwRLCnIRpIRxkJu+vevgkCpoeBq3lW0Yk3UhDMFALbxieyP3FR3s14vpk9Ty8dwNG+VHpc+bty9SyKeSNwEouJE6QAwqbHm78hxzxMBNImB7/7a3ta6v9qxj8bJhn1IWDkVJhO7YvCdZfHp6Dg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(136003)(396003)(39860400002)(376002)(451199015)(36840700001)(46966006)(40470700004)(426003)(478600001)(110136005)(54906003)(316002)(6636002)(4326008)(40480700001)(8676002)(70206006)(70586007)(6666004)(107886003)(6286002)(41300700001)(26005)(7696005)(82310400005)(36756003)(8936002)(5660300002)(86362001)(356005)(1076003)(16526019)(186003)(7636003)(336012)(82740400003)(47076005)(2906002)(40460700003)(2616005)(55016003)(36860700001)(83380400001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2022 11:49:44.3651 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da507ad4-c56c-4b06-80ca-08daadda2fe8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT071.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5824 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org HWS table resides under the context object, each context can have multiple tables with different steering types RX/TX/FDB. The table is not only a logical object but it is also represented in the HW, packets can be steered to the table and from there to other tables. Signed-off-by: Erez Shitrit Signed-off-by: Alex Vesker --- drivers/net/mlx5/hws/mlx5dr_table.c | 248 ++++++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_table.h | 44 +++++ 2 files changed, 292 insertions(+) create mode 100644 drivers/net/mlx5/hws/mlx5dr_table.c create mode 100644 drivers/net/mlx5/hws/mlx5dr_table.h diff --git a/drivers/net/mlx5/hws/mlx5dr_table.c b/drivers/net/mlx5/hws/mlx5dr_table.c new file mode 100644 index 0000000000..d3f77e4780 --- /dev/null +++ b/drivers/net/mlx5/hws/mlx5dr_table.c @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2022 NVIDIA Corporation & Affiliates + */ + +#include "mlx5dr_internal.h" + +static void mlx5dr_table_init_next_ft_attr(struct mlx5dr_table *tbl, + struct mlx5dr_cmd_ft_create_attr *ft_attr) +{ + ft_attr->type = tbl->fw_ft_type; + if (tbl->type == MLX5DR_TABLE_TYPE_FDB) + ft_attr->level = tbl->ctx->caps->fdb_ft.max_level - 1; + else + ft_attr->level = tbl->ctx->caps->nic_ft.max_level - 1; + ft_attr->rtc_valid = true; +} + +/* Call this under ctx->ctrl_lock */ +static int +mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl) +{ + struct mlx5dr_cmd_ft_create_attr ft_attr = {0}; + struct mlx5dr_cmd_forward_tbl *default_miss; + struct mlx5dr_context *ctx = tbl->ctx; + uint8_t tbl_type = tbl->type; + uint32_t vport; + + if (tbl->type != MLX5DR_TABLE_TYPE_FDB) + return 0; + + if (ctx->common_res[tbl_type].default_miss) { + ctx->common_res[tbl_type].default_miss->refcount++; + return 0; + } + + ft_attr.type = tbl->fw_ft_type; + ft_attr.level = tbl->ctx->caps->fdb_ft.max_level; /* The last level */ + ft_attr.rtc_valid = false; + + assert(ctx->caps->eswitch_manager); + vport = ctx->caps->eswitch_manager_vport_number; + + default_miss = mlx5dr_cmd_miss_ft_create(ctx->ibv_ctx, &ft_attr, vport); + if (!default_miss) { + DR_LOG(ERR, "Failed to default miss table type: 0x%x", tbl_type); + return rte_errno; + } + + ctx->common_res[tbl_type].default_miss = default_miss; + ctx->common_res[tbl_type].default_miss->refcount++; + return 0; +} + +/* Called under pthread_spin_lock(&ctx->ctrl_lock) */ +static void mlx5dr_table_down_default_fdb_miss_tbl(struct mlx5dr_table *tbl) +{ + struct mlx5dr_cmd_forward_tbl *default_miss; + struct mlx5dr_context *ctx = tbl->ctx; + uint8_t tbl_type = tbl->type; + + if (tbl->type != MLX5DR_TABLE_TYPE_FDB) + return; + + default_miss = ctx->common_res[tbl_type].default_miss; + if (--default_miss->refcount) + return; + + mlx5dr_cmd_miss_ft_destroy(default_miss); + + simple_free(default_miss); + ctx->common_res[tbl_type].default_miss = NULL; +} + +static int +mlx5dr_table_connect_to_default_miss_tbl(struct mlx5dr_table *tbl, + struct mlx5dr_devx_obj *ft) +{ + struct mlx5dr_cmd_ft_modify_attr ft_attr = {0}; + int ret; + + assert(tbl->type == MLX5DR_TABLE_TYPE_FDB); + + mlx5dr_cmd_set_attr_connect_miss_tbl(tbl->ctx, + tbl->fw_ft_type, + tbl->type, + &ft_attr); + + /* Connect to next */ + ret = mlx5dr_cmd_flow_table_modify(ft, &ft_attr); + if (ret) { + DR_LOG(ERR, "Failed to connect FT to default FDB FT"); + return errno; + } + + return 0; +} + +struct mlx5dr_devx_obj * +mlx5dr_table_create_default_ft(struct mlx5dr_table *tbl) +{ + struct mlx5dr_cmd_ft_create_attr ft_attr = {0}; + struct mlx5dr_devx_obj *ft_obj; + int ret; + + mlx5dr_table_init_next_ft_attr(tbl, &ft_attr); + + ft_obj = mlx5dr_cmd_flow_table_create(tbl->ctx->ibv_ctx, &ft_attr); + if (ft_obj && tbl->type == MLX5DR_TABLE_TYPE_FDB) { + /* Take/create ref over the default miss */ + ret = mlx5dr_table_up_default_fdb_miss_tbl(tbl); + if (ret) { + DR_LOG(ERR, "Failed to get default fdb miss"); + goto free_ft_obj; + } + ret = mlx5dr_table_connect_to_default_miss_tbl(tbl, ft_obj); + if (ret) { + DR_LOG(ERR, "Failed connecting to default miss tbl"); + goto down_miss_tbl; + } + } + + return ft_obj; + +down_miss_tbl: + mlx5dr_table_down_default_fdb_miss_tbl(tbl); +free_ft_obj: + mlx5dr_cmd_destroy_obj(ft_obj); + return NULL; +} + +void mlx5dr_table_destroy_default_ft(struct mlx5dr_table *tbl, + struct mlx5dr_devx_obj *ft_obj) +{ + mlx5dr_table_down_default_fdb_miss_tbl(tbl); + mlx5dr_cmd_destroy_obj(ft_obj); +} + +static int mlx5dr_table_init(struct mlx5dr_table *tbl) +{ + struct mlx5dr_context *ctx = tbl->ctx; + int ret; + + if (mlx5dr_table_is_root(tbl)) + return 0; + + if (!(tbl->ctx->flags & MLX5DR_CONTEXT_FLAG_HWS_SUPPORT)) { + DR_LOG(ERR, "HWS not supported, cannot create mlx5dr_table"); + rte_errno = EOPNOTSUPP; + return rte_errno; + } + + switch (tbl->type) { + case MLX5DR_TABLE_TYPE_NIC_RX: + tbl->fw_ft_type = FS_FT_NIC_RX; + break; + case MLX5DR_TABLE_TYPE_NIC_TX: + tbl->fw_ft_type = FS_FT_NIC_TX; + break; + case MLX5DR_TABLE_TYPE_FDB: + tbl->fw_ft_type = FS_FT_FDB; + break; + default: + assert(0); + break; + } + + pthread_spin_lock(&ctx->ctrl_lock); + tbl->ft = mlx5dr_table_create_default_ft(tbl); + if (!tbl->ft) { + DR_LOG(ERR, "Failed to create flow table devx object"); + pthread_spin_unlock(&ctx->ctrl_lock); + return rte_errno; + } + + ret = mlx5dr_action_get_default_stc(ctx, tbl->type); + if (ret) + goto tbl_destroy; + pthread_spin_unlock(&ctx->ctrl_lock); + + return 0; + +tbl_destroy: + mlx5dr_table_destroy_default_ft(tbl, tbl->ft); + pthread_spin_unlock(&ctx->ctrl_lock); + return rte_errno; +} + +static void mlx5dr_table_uninit(struct mlx5dr_table *tbl) +{ + if (mlx5dr_table_is_root(tbl)) + return; + pthread_spin_lock(&tbl->ctx->ctrl_lock); + mlx5dr_action_put_default_stc(tbl->ctx, tbl->type); + mlx5dr_table_destroy_default_ft(tbl, tbl->ft); + pthread_spin_unlock(&tbl->ctx->ctrl_lock); +} + +struct mlx5dr_table *mlx5dr_table_create(struct mlx5dr_context *ctx, + struct mlx5dr_table_attr *attr) +{ + struct mlx5dr_table *tbl; + int ret; + + if (attr->type > MLX5DR_TABLE_TYPE_FDB) { + DR_LOG(ERR, "Invalid table type %d", attr->type); + return NULL; + } + + tbl = simple_malloc(sizeof(*tbl)); + if (!tbl) { + rte_errno = ENOMEM; + return NULL; + } + + tbl->ctx = ctx; + tbl->type = attr->type; + tbl->level = attr->level; + LIST_INIT(&tbl->head); + + ret = mlx5dr_table_init(tbl); + if (ret) { + DR_LOG(ERR, "Failed to initialise table"); + goto free_tbl; + } + + pthread_spin_lock(&ctx->ctrl_lock); + LIST_INSERT_HEAD(&ctx->head, tbl, next); + pthread_spin_unlock(&ctx->ctrl_lock); + + return tbl; + +free_tbl: + simple_free(tbl); + return NULL; +} + +int mlx5dr_table_destroy(struct mlx5dr_table *tbl) +{ + struct mlx5dr_context *ctx = tbl->ctx; + + pthread_spin_lock(&ctx->ctrl_lock); + LIST_REMOVE(tbl, next); + pthread_spin_unlock(&ctx->ctrl_lock); + mlx5dr_table_uninit(tbl); + simple_free(tbl); + + return 0; +} diff --git a/drivers/net/mlx5/hws/mlx5dr_table.h b/drivers/net/mlx5/hws/mlx5dr_table.h new file mode 100644 index 0000000000..786dddfaa4 --- /dev/null +++ b/drivers/net/mlx5/hws/mlx5dr_table.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2022 NVIDIA Corporation & Affiliates + */ + +#ifndef MLX5DR_TABLE_H_ +#define MLX5DR_TABLE_H_ + +#define MLX5DR_ROOT_LEVEL 0 + +struct mlx5dr_table { + struct mlx5dr_context *ctx; + struct mlx5dr_devx_obj *ft; + enum mlx5dr_table_type type; + uint32_t fw_ft_type; + uint32_t level; + LIST_HEAD(matcher_head, mlx5dr_matcher) head; + LIST_ENTRY(mlx5dr_table) next; +}; + +static inline +uint32_t mlx5dr_table_get_res_fw_ft_type(enum mlx5dr_table_type tbl_type, + bool is_mirror) +{ + if (tbl_type == MLX5DR_TABLE_TYPE_NIC_RX) + return FS_FT_NIC_RX; + else if (tbl_type == MLX5DR_TABLE_TYPE_NIC_TX) + return FS_FT_NIC_TX; + else if (tbl_type == MLX5DR_TABLE_TYPE_FDB) + return is_mirror ? FS_FT_FDB_TX : FS_FT_FDB_RX; + + assert(0); + return 0; +} + +static inline bool mlx5dr_table_is_root(struct mlx5dr_table *tbl) +{ + return (tbl->level == MLX5DR_ROOT_LEVEL); +} + +struct mlx5dr_devx_obj *mlx5dr_table_create_default_ft(struct mlx5dr_table *tbl); + +void mlx5dr_table_destroy_default_ft(struct mlx5dr_table *tbl, + struct mlx5dr_devx_obj *ft_obj); +#endif /* MLX5DR_TABLE_H_ */