From patchwork Tue Oct 11 12:01:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117921 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E6AEA0545; Tue, 11 Oct 2022 14:03:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7248842CCB; Tue, 11 Oct 2022 14:03:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C5F0E42B7D for ; Tue, 11 Oct 2022 14:03:53 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29B1Na3t011947; Tue, 11 Oct 2022 05:01:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=YwJP4LnOkqqCFpsdjvFtEoi9bFXiveK7Y7MoreG2D9o=; b=JMsVnqYoHC/QHem3iBHGZyKgkPzm0Mqtzo68DWSwL4zmzPz86k92DUe9kvh0AMaWgOL/ xxvZitf3fZ+jUg5jQ+gsVnv4+3izKKnc/p0Q2I4mswwr5TWMSuy0Eu/WpB3EFaf9BWay pa2CWkSHeeShPSAff3jLvw3Pu4qA51Vt/0stuNMI6v+uV3GyUXL2VK6ofcgMBJdcb2c2 eB47Cs51SuswyzY/1WWIpuVr1zWKQuX6Yv2qsYA3MGQcwT8cPLNc8bQ3CHcfpo1SnyPw TMCrW2uAyGCXW6z5lqSCXIOjrMc6cO6C0WDPCEF6592w38mYK1ev7VuC8do/xs+yrBcm 5g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4y26k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 11 Oct 2022 05:01:45 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 11 Oct 2022 05:01:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:01:43 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 5B2343F705A; Tue, 11 Oct 2022 05:01:41 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 02/13] common/cnxk: add devargs for soft expiry poll frequency Date: Tue, 11 Oct 2022 17:31:24 +0530 Message-ID: <20221011120135.45846-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: RLcJsHeRVAXpqEmgOG9BdVQp7TWhM3xb X-Proofpoint-GUID: RLcJsHeRVAXpqEmgOG9BdVQp7TWhM3xb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support to override soft expiry poll frequency via devargs. Also provide helper API to indicate reassembly support on a chip and documentation for devargs that are already present. Signed-off-by: Nithin Dabilpuram --- doc/guides/nics/cnxk.rst | 39 +++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.c | 7 +++++ drivers/common/cnxk/roc_nix_inl.h | 3 ++- drivers/common/cnxk/roc_nix_inl_dev.c | 4 +-- drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cnxk_ethdev_sec.c | 17 +++++++++--- 6 files changed, 65 insertions(+), 6 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index a1e3a4a965..7da6cb3967 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -494,6 +494,45 @@ Runtime Config Options for inline device With the above configuration, application can enable inline IPsec processing for inbound SA with max SPI of 128 for traffic aggregated on inline device. +- ``Count of meta buffers for inline inbound IPsec second pass`` + + Number of meta buffers allocated for inline inbound IPsec second pass can + be specified by ``nb_meta_bufs`` ``devargs`` parameter. Default value is + computed runtime based on pkt mbuf pools created and in use. Number of meta + buffers should be at least equal to aggregated number of packet buffers of all + packet mbuf pools in use by Inline IPsec enabled ethernet devices. + + For example:: + + -a 0002:1d:00.0,nb_meta_bufs=1024 + + With the above configuration, PMD would enable inline IPsec processing + for inbound with 1024 meta buffers available for second pass. + +- ``Meta buffer size for inline inbound IPsec second pass`` + + Size of meta buffer allocated for inline inbound IPsec second pass can + be specified by ``meta_buf_sz`` ``devargs`` parameter. Default value is + computed runtime based on pkt mbuf pools created and in use. + + For example:: + + -a 0002:1d:00.0,meta_buf_sz=512 + + With the above configuration, PMD would allocate meta buffers of size 512 for + inline inbound IPsec processing second pass. + +- ``Inline Outbound soft expiry poll frequency in usec`` (default ``100``) + + Soft expiry poll frequency for Inline Outbound sessions can be specified by + ``soft_exp_poll_freq`` ``devargs`` parameter. + + For example:: + + -a 0002:1d:00.0,soft_exp_poll_freq=1000 + + With the above configuration, driver would poll for soft expiry events every + 1000 usec. Debugging Options ----------------- diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index cdf31b1f0c..213d71e684 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -480,6 +480,13 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable) return mbox_process(mbox); } +bool +roc_nix_has_reass_support(struct roc_nix *nix) +{ + PLT_SET_USED(nix); + return !!roc_model_is_cn10ka(); +} + int roc_nix_inl_inb_init(struct roc_nix *roc_nix) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 019cf6d28b..c537262819 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -183,7 +183,7 @@ struct roc_nix_inl_dev { uint16_t wqe_skip; uint8_t spb_drop_pc; uint8_t lpb_drop_pc; - bool set_soft_exp_poll; + uint32_t soft_exp_poll_freq; /* Polling disabled if 0 */ uint32_t nb_meta_bufs; uint32_t meta_buf_sz; /* End of input parameters */ @@ -229,6 +229,7 @@ int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev); int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena); int __roc_api roc_nix_inl_meta_aura_check(struct roc_nix_rq *rq); +bool __roc_api roc_nix_has_reass_support(struct roc_nix *nix); /* NIX Inline Outbound API */ int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 4fe7b5180b..c3d94dd0da 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -789,7 +789,6 @@ nix_inl_outb_poll_thread_setup(struct nix_inl_dev *inl_dev) soft_exp_consumer_cnt = 0; soft_exp_poll_thread_exit = false; - inl_dev->soft_exp_poll_freq = 100; rc = plt_ctrl_thread_create(&inl_dev->soft_exp_poll_thread, "OUTB_SOFT_EXP_POLL_THREAD", NULL, nix_inl_outb_poll_thread, inl_dev); @@ -839,10 +838,11 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev) inl_dev->wqe_skip = roc_inl_dev->wqe_skip; inl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT; inl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT; - inl_dev->set_soft_exp_poll = roc_inl_dev->set_soft_exp_poll; + inl_dev->set_soft_exp_poll = !!roc_inl_dev->soft_exp_poll_freq; inl_dev->nb_rqs = inl_dev->is_multi_channel ? 1 : PLT_MAX_ETHPORTS; inl_dev->nb_meta_bufs = roc_inl_dev->nb_meta_bufs; inl_dev->meta_buf_sz = roc_inl_dev->meta_buf_sz; + inl_dev->soft_exp_poll_freq = roc_inl_dev->soft_exp_poll_freq; if (roc_inl_dev->spb_drop_pc) inl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 276fec3660..f08b6076e4 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -135,6 +135,7 @@ INTERNAL { roc_nix_get_pf_func; roc_nix_get_vf; roc_nix_get_vwqe_interval; + roc_nix_has_reass_support; roc_nix_inl_cb_register; roc_nix_inl_cb_unregister; roc_nix_inl_ctx_write; diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index 9304b1465d..8bec9acb54 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -12,6 +12,10 @@ #define CNXK_INL_CPT_CHANNEL "inl_cpt_channel" #define CNXK_NIX_INL_NB_META_BUFS "nb_meta_bufs" #define CNXK_NIX_INL_META_BUF_SZ "meta_buf_sz" +#define CNXK_NIX_SOFT_EXP_POLL_FREQ "soft_exp_poll_freq" + +/* Default soft expiry poll freq in usec */ +#define CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT 100 struct inl_cpt_channel { bool is_multi_channel; @@ -263,6 +267,7 @@ static int nix_inl_parse_devargs(struct rte_devargs *devargs, struct roc_nix_inl_dev *inl_dev) { + uint32_t soft_exp_poll_freq = CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT; uint32_t ipsec_in_max_spi = BIT(8) - 1; uint32_t ipsec_in_min_spi = 0; struct inl_cpt_channel cpt_channel; @@ -292,6 +297,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, &nb_meta_bufs); rte_kvargs_process(kvlist, CNXK_NIX_INL_META_BUF_SZ, &parse_val_u32, &meta_buf_sz); + rte_kvargs_process(kvlist, CNXK_NIX_SOFT_EXP_POLL_FREQ, + &parse_val_u32, &soft_exp_poll_freq); rte_kvargs_free(kvlist); null_devargs: @@ -303,6 +310,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, inl_dev->is_multi_channel = cpt_channel.is_multi_channel; inl_dev->nb_meta_bufs = nb_meta_bufs; inl_dev->meta_buf_sz = meta_buf_sz; + inl_dev->soft_exp_poll_freq = soft_exp_poll_freq; return 0; exit: return -EINVAL; @@ -390,7 +398,6 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv, wqe_skip = RTE_ALIGN_CEIL(sizeof(struct rte_mbuf), ROC_CACHE_LINE_SZ); wqe_skip = wqe_skip / ROC_CACHE_LINE_SZ; inl_dev->wqe_skip = wqe_skip; - inl_dev->set_soft_exp_poll = true; rc = roc_nix_inl_dev_init(inl_dev); if (rc) { plt_err("Failed to init nix inl device, rc=%d(%s)", rc, @@ -425,5 +432,9 @@ RTE_PMD_REGISTER_KMOD_DEP(cnxk_nix_inl, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(cnxk_nix_inl, CNXK_NIX_INL_SELFTEST "=1" - CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-65535>" - CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>"); + CNXK_NIX_INL_IPSEC_IN_MIN_SPI "=<1-U32_MAX>" + CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-U32_MAX>" + CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>" + CNXK_NIX_INL_NB_META_BUFS "=<1-U32_MAX>" + CNXK_NIX_INL_META_BUF_SZ "=<1-U32_MAX>" + CNXK_NIX_SOFT_EXP_POLL_FREQ "=<0-U32_MAX>");