From patchwork Tue Oct 11 12:01:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117909 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3956A0547; Tue, 11 Oct 2022 14:01:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9964842DBA; Tue, 11 Oct 2022 14:01:49 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A72CA42D42 for ; Tue, 11 Oct 2022 14:01:48 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29B9eJgG008912 for ; Tue, 11 Oct 2022 05:01:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=OR2jBpap/Y8Kt/qKqism7DwyWjJax3oskGnaTP1SKZ8=; b=ZfD1y2XJIESNL/xTdCuscDVeyWAB+/O/HGmB7/36P2wq2AOlKpSY6q/ZGnSTis73Vka8 4oOZELfffZ5+XTJwArg01ZeCDX5E/I/fIEPIjC6KErc1PKiXMhVGLnYnORbbi9j5YjF1 zOKXGjsAi+NAK76g7PmZnwNUmcn/HA60ozwyNQK3el8MBKdAukehAzittv+OtTt34MBt lFlpLKDrd01Al8FbxsJ3ifRjqb/s2jFAwCSGb0nwJxI/abmr9RqL073yOJntXo6T6LNJ 7tFo77O4/lsXEgF3BuRisvU3F/FekBIZyOqkiSPvxgZvbgH+GxWJaY2ZZeLB4WbS5f7a Eg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4y26f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Oct 2022 05:01:42 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Oct 2022 05:01:40 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:01:40 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 8957F3F7040; Tue, 11 Oct 2022 05:01:38 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Sathesh Edara Subject: [PATCH 01/13] common/cnxk: set MTU size on SDP based on SoC type Date: Tue, 11 Oct 2022 17:31:23 +0530 Message-ID: <20221011120135.45846-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: aszLtfhV8ZbstN5-JAFWpk7r17lgU91E X-Proofpoint-GUID: aszLtfhV8ZbstN5-JAFWpk7r17lgU91E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sathesh Edara Set maximum frame size on SDP NIX side to 16KB for T93 A0-B0, F95N A0 and F95O A0 SOC type. Rest of the SoCs SDP NIX to 64KB. Signed-off-by: Sathesh Edara --- drivers/common/cnxk/hw/nix.h | 1 + drivers/common/cnxk/roc_errata.h | 8 ++++++++ drivers/common/cnxk/roc_model.h | 12 ++++++++++++ drivers/common/cnxk/roc_nix.c | 5 ++++- 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index a5352644ca..425c335bf3 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2118,6 +2118,7 @@ struct nix_lso_format { #define NIX_CN9K_MAX_HW_FRS 9212UL #define NIX_LBK_MAX_HW_FRS 65535UL #define NIX_SDP_MAX_HW_FRS 65535UL +#define NIX_SDP_16K_HW_FRS 16380UL #define NIX_RPM_MAX_HW_FRS 16380UL #define NIX_MIN_HW_FRS 60UL diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h index d3b32f1786..a39796e894 100644 --- a/drivers/common/cnxk/roc_errata.h +++ b/drivers/common/cnxk/roc_errata.h @@ -90,4 +90,12 @@ roc_errata_nix_no_meta_aura(void) return roc_model_is_cn10ka_a0(); } +/* Errata IPBUNIXTX-35039 */ +static inline bool +roc_errata_nix_sdp_send_has_mtu_size_16k(void) +{ + return (roc_model_is_cnf95xxn_a0() || roc_model_is_cnf95xxo_a0() || + roc_model_is_cn96_a0() || roc_model_is_cn96_b0()); +} + #endif /* _ROC_ERRATA_H_ */ diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index 57a8af06fc..1985dd771d 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -140,6 +140,12 @@ roc_model_is_cn96_ax(void) return (roc_model->flag & ROC_MODEL_CN96xx_Ax); } +static inline uint64_t +roc_model_is_cn96_b0(void) +{ + return (roc_model->flag & ROC_MODEL_CN96xx_B0); +} + static inline uint64_t roc_model_is_cn96_cx(void) { @@ -170,6 +176,12 @@ roc_model_is_cnf95xxn_b0(void) return roc_model->flag & ROC_MODEL_CNF95xxN_B0; } +static inline uint64_t +roc_model_is_cnf95xxo_a0(void) +{ + return roc_model->flag & ROC_MODEL_CNF95xxO_A0; +} + static inline uint16_t roc_model_is_cn95xxn_a0(void) { diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 4bb306b60e..8fd8ec8461 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -127,8 +127,11 @@ roc_nix_max_pkt_len(struct roc_nix *roc_nix) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); - if (roc_nix_is_sdp(roc_nix)) + if (roc_nix_is_sdp(roc_nix)) { + if (roc_errata_nix_sdp_send_has_mtu_size_16k()) + return NIX_SDP_16K_HW_FRS; return NIX_SDP_MAX_HW_FRS; + } if (roc_model_is_cn9k()) return NIX_CN9K_MAX_HW_FRS;