diff mbox series

[01/35] net/ionic: fix up endianness for Rx and Tx handling

Message ID 20221007174336.54354-2-andrew.boyer@amd.com (mailing list archive)
State Superseded, archived
Delegated to: Ferruh Yigit
Headers
Series net/ionic: updates for 22.11 release |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-testing warning apply patch failure

Commit Message

Andrew Boyer Oct. 7, 2022, 5:43 p.m. UTC 
  These fields all need to be LE when talking to the FW.

Fixes: a27d901331da ("net/ionic: add Rx and Tx handling")
Cc: cardigliano@ntop.org
Cc: stable@dpdk.org

Signed-off-by: Andrew Boyer <andrew.boyer@amd.com>
---
 drivers/net/ionic/ionic_rxtx.c | 27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c
index 9f602de6a9..af2d89f9fa 100644
--- a/drivers/net/ionic/ionic_rxtx.c
+++ b/drivers/net/ionic/ionic_rxtx.c
@@ -300,18 +300,20 @@  ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,
 		bool start, bool done)
 {
 	void **info;
+	uint64_t cmd;
 	uint8_t flags = 0;
 	flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
 	flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
 	flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
 	flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
 
-	desc->cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO,
+	cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO,
 		flags, nsge, addr);
-	desc->len = len;
-	desc->vlan_tci = vlan_tci;
-	desc->hdr_len = hdrlen;
-	desc->mss = mss;
+	desc->cmd = rte_cpu_to_le_64(cmd);
+	desc->len = rte_cpu_to_le_16(len);
+	desc->vlan_tci = rte_cpu_to_le_16(vlan_tci);
+	desc->hdr_len = rte_cpu_to_le_16(hdrlen);
+	desc->mss = rte_cpu_to_le_16(mss);
 
 	if (done) {
 		info = IONIC_INFO_PTR(q, q->head_idx);
@@ -423,7 +425,7 @@  ionic_tx_tso(struct ionic_tx_qcq *txq, struct rte_mbuf *txm)
 				len = RTE_MIN(frag_left, left);
 				frag_left -= len;
 				elem->addr = next_addr;
-				elem->len = len;
+				elem->len = rte_cpu_to_le_16(len);
 				elem++;
 				desc_nsge++;
 			} else {
@@ -470,7 +472,7 @@  ionic_tx(struct ionic_tx_qcq *txq, struct rte_mbuf *txm)
 	bool encap;
 	bool has_vlan;
 	uint64_t ol_flags = txm->ol_flags;
-	uint64_t addr;
+	uint64_t addr, cmd;
 	uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE;
 	uint8_t flags = 0;
 
@@ -505,9 +507,10 @@  ionic_tx(struct ionic_tx_qcq *txq, struct rte_mbuf *txm)
 
 	addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm));
 
-	desc->cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr);
-	desc->len = txm->data_len;
-	desc->vlan_tci = txm->vlan_tci;
+	cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr);
+	desc->cmd = rte_cpu_to_le_64(cmd);
+	desc->len = rte_cpu_to_le_16(txm->data_len);
+	desc->vlan_tci = rte_cpu_to_le_16(txm->vlan_tci);
 
 	info[0] = txm;
 
@@ -515,7 +518,7 @@  ionic_tx(struct ionic_tx_qcq *txq, struct rte_mbuf *txm)
 
 	txm_seg = txm->next;
 	while (txm_seg != NULL) {
-		elem->len = txm_seg->data_len;
+		elem->len = rte_cpu_to_le_16(txm_seg->data_len);
 		elem->addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm_seg));
 		elem++;
 		txm_seg = txm_seg->next;
@@ -845,7 +848,7 @@  ionic_rx_clean(struct ionic_rx_qcq *rxq,
 	/* Vlan Strip */
 	if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN) {
 		pkt_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
-		rxm->vlan_tci = cq_desc->vlan_tci;
+		rxm->vlan_tci = rte_le_to_cpu_16(cq_desc->vlan_tci);
 	}
 
 	/* Checksum */