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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT055.mail.protection.outlook.com (10.13.175.129) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Fri, 7 Oct 2022 17:44:37 +0000 Received: from driver-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Fri, 7 Oct 2022 12:44:36 -0500 From: Andrew Boyer To: CC: Andrew Boyer Subject: [PATCH 13/35] net/ionic: only request notifyq interrupt if supported Date: Fri, 7 Oct 2022 10:43:14 -0700 Message-ID: <20221007174336.54354-14-andrew.boyer@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221007174336.54354-1-andrew.boyer@amd.com> References: <20221007174336.54354-1-andrew.boyer@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT055:EE_|CH3PR12MB7642:EE_ X-MS-Office365-Filtering-Correlation-Id: 265e2ccb-c526-4656-659f-08daa88b9aef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This prevents spurious interrupts on virtual platforms. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_lif.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index 4cc44a6a2f..220a4fdacb 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -1350,6 +1350,7 @@ ionic_lif_notifyq_init(struct ionic_lif *lif) struct ionic_dev *idev = &lif->adapter->idev; struct ionic_notify_qcq *nqcq = lif->notifyqcq; struct ionic_queue *q = &nqcq->qcq.q; + uint16_t flags = IONIC_QINIT_F_ENA; int err; struct ionic_admin_ctx ctx = { @@ -1359,14 +1360,19 @@ ionic_lif_notifyq_init(struct ionic_lif *lif) .type = q->type, .ver = lif->qtype_info[q->type].version, .index = rte_cpu_to_le_32(q->index), - .intr_index = rte_cpu_to_le_16(nqcq->intr.index), - .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ | - IONIC_QINIT_F_ENA), + .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), .ring_size = rte_log2_u32(q->num_descs), .ring_base = rte_cpu_to_le_64(q->base_pa), } }; + /* Only enable an interrupt if the device supports them */ + if (lif->adapter->intf->configure_intr != NULL) { + flags |= IONIC_QINIT_F_IRQ; + ctx.cmd.q_init.intr_index = rte_cpu_to_le_16(nqcq->intr.index); + } + ctx.cmd.q_init.flags = rte_cpu_to_le_16(flags); + IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index); IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa); IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",