diff mbox series

[v2,1/3] event/cnxk: avoid reading non cached registers

Message ID 20220921061558.3747-1-pbhagavatula@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers
Series [v2,1/3] event/cnxk: avoid reading non cached registers |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Pavan Nikhilesh Bhagavatula Sept. 21, 2022, 6:15 a.m. UTC 
  From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Avoid reading non-cached registers in fastpath.
PENDSTATE need not be read before tag flush in tx enqueue
context as we have additional checks prior to check for
pending flushes.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 Depends-on: Series-24634

 v2 Changes:
 - Rebase on next-net-mrvl

 drivers/event/cnxk/cn9k_worker.h | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

--
2.25.1
diff mbox series

Patch

diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h
index 384b428ed1..881861f348 100644
--- a/drivers/event/cnxk/cn9k_worker.h
+++ b/drivers/event/cnxk/cn9k_worker.h
@@ -156,6 +156,15 @@  cn9k_sso_hws_dual_forward_event(struct cn9k_sso_hws_dual *dws, uint64_t base,
 	}
 }

+static __rte_always_inline void
+cn9k_sso_tx_tag_flush(uint64_t base)
+{
+	if (unlikely(CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_TAG)) ==
+		     SSO_TT_EMPTY))
+		return;
+	plt_write64(0, base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
+}
+
 static __rte_always_inline void
 cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
 		 const uint32_t tag, const uint32_t flags,
@@ -835,7 +844,7 @@  cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,
 			return 1;
 	}

-	cnxk_sso_hws_swtag_flush(base);
+	cn9k_sso_tx_tag_flush(base);

 	return 1;
 }