[v5,1/7] eal/loongarch: support LoongArch architecture
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Commit Message
Add all necessary elements for DPDK to compile and run EAL on
LoongArch64 Soc.
This includes:
- EAL library implementation for LoongArch ISA.
- meson build structure for 'loongarch' architecture.
RTE_ARCH_LOONGARCH define is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in
the current version for LoongArch.
Compilation was tested on Debian and CentOS using loongarch64
cross-compile toolchain from x86 build hosts. Funtions were tested
on Loongnix and Kylin which are two Linux distributions supported
LoongArch host based on Linux 4.19 maintained by Loongson
Corporation.
We also tested DPDK on LoongArch with some external applications,
including: Pktgen-DPDK, OVS, VPP.
The platform is currently marked as linux-only because there is no
other OS than Linux support LoongArch host currently.
The i40e PMD driver is disabled on LoongArch because of the absence
of vector support in the current version.
Similar to RISC-V, the compilation of following modules has been
disabled by this commit and will be re-enabled in later commits as
fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
MAINTAINERS | 6 +
app/test/test_xmmt_ops.h | 12 +
.../loongarch/loongarch_loongarch64_linux_gcc | 16 ++
config/loongarch/meson.build | 43 +++
doc/guides/contributing/design.rst | 2 +-
.../cross_build_dpdk_for_loongarch.rst | 87 ++++++
doc/guides/linux_gsg/index.rst | 1 +
doc/guides/nics/features.rst | 6 +
doc/guides/nics/features/default.ini | 1 +
doc/guides/rel_notes/release_22_11.rst | 6 +
drivers/net/i40e/meson.build | 6 +
drivers/net/ixgbe/meson.build | 6 +
drivers/net/memif/meson.build | 6 +
drivers/net/tap/meson.build | 6 +
examples/l3fwd/meson.build | 6 +
lib/eal/linux/eal_memory.c | 4 +
lib/eal/loongarch/include/meson.build | 21 ++
lib/eal/loongarch/include/rte_atomic.h | 253 ++++++++++++++++++
lib/eal/loongarch/include/rte_byteorder.h | 46 ++++
lib/eal/loongarch/include/rte_cpuflags.h | 39 +++
lib/eal/loongarch/include/rte_cycles.h | 53 ++++
lib/eal/loongarch/include/rte_io.h | 18 ++
lib/eal/loongarch/include/rte_mcslock.h | 18 ++
lib/eal/loongarch/include/rte_memcpy.h | 61 +++++
lib/eal/loongarch/include/rte_pause.h | 24 ++
lib/eal/loongarch/include/rte_pflock.h | 17 ++
.../loongarch/include/rte_power_intrinsics.h | 20 ++
lib/eal/loongarch/include/rte_prefetch.h | 47 ++++
lib/eal/loongarch/include/rte_rwlock.h | 42 +++
lib/eal/loongarch/include/rte_spinlock.h | 90 +++++++
lib/eal/loongarch/include/rte_ticketlock.h | 18 ++
lib/eal/loongarch/include/rte_vect.h | 65 +++++
lib/eal/loongarch/meson.build | 11 +
lib/eal/loongarch/rte_cpuflags.c | 94 +++++++
lib/eal/loongarch/rte_cycles.c | 45 ++++
lib/eal/loongarch/rte_hypervisor.c | 11 +
lib/eal/loongarch/rte_power_intrinsics.c | 51 ++++
meson.build | 2 +
38 files changed, 1259 insertions(+), 1 deletion(-)
create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc
create mode 100644 config/loongarch/meson.build
create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
create mode 100644 lib/eal/loongarch/include/meson.build
create mode 100644 lib/eal/loongarch/include/rte_atomic.h
create mode 100644 lib/eal/loongarch/include/rte_byteorder.h
create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h
create mode 100644 lib/eal/loongarch/include/rte_cycles.h
create mode 100644 lib/eal/loongarch/include/rte_io.h
create mode 100644 lib/eal/loongarch/include/rte_mcslock.h
create mode 100644 lib/eal/loongarch/include/rte_memcpy.h
create mode 100644 lib/eal/loongarch/include/rte_pause.h
create mode 100644 lib/eal/loongarch/include/rte_pflock.h
create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h
create mode 100644 lib/eal/loongarch/include/rte_prefetch.h
create mode 100644 lib/eal/loongarch/include/rte_rwlock.h
create mode 100644 lib/eal/loongarch/include/rte_spinlock.h
create mode 100644 lib/eal/loongarch/include/rte_ticketlock.h
create mode 100644 lib/eal/loongarch/include/rte_vect.h
create mode 100644 lib/eal/loongarch/meson.build
create mode 100644 lib/eal/loongarch/rte_cpuflags.c
create mode 100644 lib/eal/loongarch/rte_cycles.c
create mode 100644 lib/eal/loongarch/rte_hypervisor.c
create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c
Comments
This is only a first pass.
On Wed, Aug 24, 2022 at 10:31 AM Min Zhou <zhoumin@loongson.cn> wrote:
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 32ffdd1a61..f00b82b5ce 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -311,6 +311,12 @@ F: config/riscv/
> F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
> F: lib/eal/riscv/
>
> +LoongArch
> +M: Min Zhou <zhoumin@loongson.cn>
> +F: config/loongarch/
> +F: doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
> +F: lib/eal/loongarch/
> +
I tried to put entries in MAINTAINERS in a pseudo alphabetical order
(ignoring the vendor name).
We currently have: ARM, Power, RISC-V, X86.
As a consequence, the block for LoongArch should be moved between ARM,
and Power arches.
> Intel x86
> M: Bruce Richardson <bruce.richardson@intel.com>
> M: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
[snip]
> diff --git a/config/loongarch/meson.build b/config/loongarch/meson.build
> new file mode 100644
> index 0000000000..e052fbad7f
> --- /dev/null
> +++ b/config/loongarch/meson.build
> @@ -0,0 +1,43 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2022 Loongson Technology Corporation Limited
> +
> +if not dpdk_conf.get('RTE_ARCH_64')
> + error('Only 64-bit compiles are supported for this platform type')
> +endif
> +dpdk_conf.set('RTE_ARCH', 'loongarch')
> +dpdk_conf.set('RTE_ARCH_LOONGARCH', 1)
> +dpdk_conf.set('RTE_ARCH_NO_VECTOR', 1)
?
RTE_ARCH_NO_VECTOR is not used anywhere, please remove.
> +
> +machine_args_generic = [
> + ['default', ['-march=loongarch64']],
> +]
> +
> +flags_generic = [
> + ['RTE_MACHINE', '"loongarch64"'],
> + ['RTE_MAX_LCORE', 64],
> + ['RTE_MAX_NUMA_NODES', 16],
> + ['RTE_CACHE_LINE_SIZE', 64]]
> +
> +impl_generic = ['Generic loongarch', flags_generic, machine_args_generic]
> +
> +machine = []
> +machine_args = []
> +
> +machine = impl_generic
> +impl_pn = 'default'
> +
> +message('Implementer : ' + machine[0])
> +foreach flag: machine[1]
> + if flag.length() > 0
> + dpdk_conf.set(flag[0], flag[1])
> + endif
> +endforeach
> +
> +foreach marg: machine[2]
> + if marg[0] == impl_pn
> + foreach f: marg[1]
> + machine_args += f
> + endforeach
> + endif
> +endforeach
> +message(machine_args)
[snip]
> diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst
> index 747552c385..c34966b241 100644
> --- a/doc/guides/linux_gsg/index.rst
> +++ b/doc/guides/linux_gsg/index.rst
> @@ -15,6 +15,7 @@ Getting Started Guide for Linux
> build_dpdk
> cross_build_dpdk_for_arm64
> cross_build_dpdk_for_riscv
> + cross_build_dpdk_for_loongarch
In alphabetical order please.
> linux_drivers
> build_sample_apps
> linux_eal_parameters
> diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst
> index 7f6cb914a5..8afa7ef7fd 100644
> --- a/doc/guides/nics/features.rst
> +++ b/doc/guides/nics/features.rst
> @@ -848,6 +848,12 @@ rv64
> Support 64-bit RISC-V architecture.
>
>
> +LoongArch64
> +-----------
> +
> +Support 64-bit LoongArch architecture.
> +
> +
Idem.
> x86-32
> ------
>
> diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini
> index d1db0c256a..8bbc4600bd 100644
> --- a/doc/guides/nics/features/default.ini
> +++ b/doc/guides/nics/features/default.ini
> @@ -73,6 +73,7 @@ ARMv7 =
> ARMv8 =
> Power8 =
> rv64 =
> +LoongArch64 =
Idem.
> x86-32 =
> x86-64 =
> Usage doc =
> diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst
> index 8c021cf050..126160d683 100644
> --- a/doc/guides/rel_notes/release_22_11.rst
> +++ b/doc/guides/rel_notes/release_22_11.rst
> @@ -55,6 +55,12 @@ New Features
> Also, make sure to start the actual text at the margin.
> =======================================================
>
> +* **Added initial LoongArch architecture support.**
> +
> + Added EAL implementation for LoongArch architecture. The initial devices
> + the porting was tested on included Loongson 3A5000, Loongson 3C5000 and
> + Loongson 3C5000L. In theory this implementation should work with any target
> + based on ``LoongArch`` ISA.
Sections in the release notes are separated with two empty lines.
>
> Removed Items
> -------------
[snip]
> diff --git a/lib/eal/loongarch/include/meson.build b/lib/eal/loongarch/include/meson.build
> new file mode 100644
> index 0000000000..d5699c5373
> --- /dev/null
> +++ b/lib/eal/loongarch/include/meson.build
> @@ -0,0 +1,21 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2022 Loongson Technology Corporation Limited
> +
> +arch_headers = files(
> + 'rte_atomic.h',
> + 'rte_byteorder.h',
> + 'rte_cpuflags.h',
> + 'rte_cycles.h',
> + 'rte_io.h',
> + 'rte_mcslock.h',
> + 'rte_memcpy.h',
> + 'rte_pause.h',
> + 'rte_pflock.h',
> + 'rte_power_intrinsics.h',
> + 'rte_prefetch.h',
> + 'rte_rwlock.h',
> + 'rte_spinlock.h',
> + 'rte_ticketlock.h',
> + 'rte_vect.h',
> +)
msclock, pflock and ticketlock are now non-arch specific headers.
They can be removed from the loongarch include directory.
See: e5e613f05b8c ("eal: remove unused arch-specific headers for locks")
> +install_headers(arch_headers, subdir: get_option('include_subdir_arch'))
> diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h
> new file mode 100644
> index 0000000000..8e007e7f76
> --- /dev/null
> +++ b/lib/eal/loongarch/include/rte_atomic.h
> @@ -0,0 +1,253 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Loongson Technology Corporation Limited
> + */
> +
> +#ifndef _RTE_ATOMIC_LOONGARCH_H_
> +#define _RTE_ATOMIC_LOONGARCH_H_
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include <stdint.h>
> +#include "generic/rte_atomic.h"
> +
> +/**
> + * LoongArch Synchronize
> + */
> +static inline void synchronize(void)
This name is too generic.
Plus all memory barriers are implemented in the same way.
I suggest defining rte_mb() as this inline helper.
> +{
> + __asm__ __volatile__("dbar 0":::"memory");
> +}
> +
> +/**
> + * General memory barrier.
> + *
> + * Guarantees that the LOAD and STORE operations generated before the
> + * barrier occur before the LOAD and STORE operations generated after.
> + * This function is architecture dependent.
Those comments are copied from the generic header which is used for
doxygen, but you don't need them in the arch specific header.
Please remove.
> + */
> +#define rte_mb() synchronize()
> +
> +/**
> + * Write memory barrier.
> + *
> + * Guarantees that the STORE operations generated before the barrier
> + * occur before the STORE operations generated after.
> + * This function is architecture dependent.
> + */
> +#define rte_wmb() synchronize()
> +
> +/**
> + * Read memory barrier.
> + *
> + * Guarantees that the LOAD operations generated before the barrier
> + * occur before the LOAD operations generated after.
> + * This function is architecture dependent.
> + */
> +#define rte_rmb() synchronize()
> +
> +#define rte_smp_mb() rte_mb()
> +
> +#define rte_smp_wmb() rte_mb()
> +
> +#define rte_smp_rmb() rte_mb()
> +
> +#define rte_io_mb() rte_mb()
> +
> +#define rte_io_wmb() rte_mb()
> +
> +#define rte_io_rmb() rte_mb()
> +
> +static __rte_always_inline void
> +rte_atomic_thread_fence(int memorder)
> +{
> + __atomic_thread_fence(memorder);
> +}
> +
> +#ifndef RTE_FORCE_INTRINSICS
Unless I missed something, there is no loongarch specific
implementations when RTE_FORCE_INTRINSICS is unset.
What is the point of supporting the case where RTE_FORCE_INTRINSICS is
undefined?
If there is no need, force-set RTE_FORCE_INTRINSICS in config and then
update headers accordingly.
> +/*------------------------- 16 bit atomic operations -------------------------*/
> +static inline int
> +rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
> +{
> + return __sync_bool_compare_and_swap(dst, exp, src);
> +}
> +
> +static inline uint16_t
> +rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
> +{
> +#if defined(__clang__)
> + return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);
> +#else
> + return __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST);
> +#endif
> +}
> +
> +static inline void
> +rte_atomic16_inc(rte_atomic16_t *v)
> +{
> + rte_atomic16_add(v, 1);
> +}
> +
> +static inline void
> +rte_atomic16_dec(rte_atomic16_t *v)
> +{
> + rte_atomic16_sub(v, 1);
> +}
> +
> +static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
> +{
> + return __sync_add_and_fetch(&v->cnt, 1) == 0;
> +}
> +
> +static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
> +{
> + return __sync_sub_and_fetch(&v->cnt, 1) == 0;
> +}
> +
> +static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
> +{
> + return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
> +}
> +
> +/*------------------------- 32 bit atomic operations -------------------------*/
> +static inline int
> +rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
> +{
> + return __sync_bool_compare_and_swap(dst, exp, src);
> +}
> +
> +static inline uint32_t
> +rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
> +{
> +#if defined(__clang__)
> + return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);
> +#else
> + return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST);
> +#endif
> +}
> +
> +static inline void
> +rte_atomic32_inc(rte_atomic32_t *v)
> +{
> + rte_atomic32_add(v, 1);
> +}
> +
> +static inline void
> +rte_atomic32_dec(rte_atomic32_t *v)
> +{
> + rte_atomic32_sub(v, 1);
> +}
> +
> +static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
> +{
> + return __sync_add_and_fetch(&v->cnt, 1) == 0;
> +}
> +
> +static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
> +{
> + return __sync_sub_and_fetch(&v->cnt, 1) == 0;
> +}
> +
> +static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
> +{
> + return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
> +}
> +
> +/*------------------------- 64 bit atomic operations -------------------------*/
> +static inline int
> +rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
> +{
> + return __sync_bool_compare_and_swap(dst, exp, src);
> +}
> +
> +static inline uint64_t
> +rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
> +{
> +#if defined(__clang__)
> + return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);
> +#else
> + return __atomic_exchange_8(dst, val, __ATOMIC_SEQ_CST);
> +#endif
> +}
> +
> +static inline void
> +rte_atomic64_init(rte_atomic64_t *v)
> +{
> + v->cnt = 0;
> +}
> +
> +static inline int64_t
> +rte_atomic64_read(rte_atomic64_t *v)
> +{
> + return v->cnt;
> +}
> +
> +static inline void
> +rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
> +{
> + v->cnt = new_value;
> +}
> +
> +static inline void
> +rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
> +{
> + __sync_fetch_and_add(&v->cnt, inc);
> +}
> +
> +static inline void
> +rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
> +{
> + __sync_fetch_and_sub(&v->cnt, dec);
> +}
> +
> +static inline void
> +rte_atomic64_inc(rte_atomic64_t *v)
> +{
> + rte_atomic64_add(v, 1);
> +}
> +
> +static inline void
> +rte_atomic64_dec(rte_atomic64_t *v)
> +{
> + rte_atomic64_sub(v, 1);
> +}
> +
> +static inline int64_t
> +rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
> +{
> + return __sync_add_and_fetch(&v->cnt, inc);
> +}
> +
> +static inline int64_t
> +rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
> +{
> + return __sync_sub_and_fetch(&v->cnt, dec);
> +}
> +
> +static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
> +{
> + return rte_atomic64_add_return(v, 1) == 0;
> +}
> +
> +static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
> +{
> + return rte_atomic64_sub_return(v, 1) == 0;
> +}
> +
> +static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
> +{
> + return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
> +}
> +
> +static inline void rte_atomic64_clear(rte_atomic64_t *v)
> +{
> + rte_atomic64_set(v, 0);
> +}
> +#endif
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* _RTE_ATOMIC_LOONGARCH_H_ */
[snip]
> diff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h
> new file mode 100644
> index 0000000000..1f8f957faf
> --- /dev/null
> +++ b/lib/eal/loongarch/include/rte_cycles.h
> @@ -0,0 +1,53 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Loongson Technology Corporation Limited
> + */
> +
> +#ifndef _RTE_CYCLES_LOONGARCH_H_
> +#define _RTE_CYCLES_LOONGARCH_H_
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include "generic/rte_cycles.h"
> +
> +static inline uint64_t
> +get_cycle_count(void)
Same comment as earlier for memory barriers, this name is too generic.
Prefer rte_rdtsc() as the name for this helper.
> +{
> + uint64_t count;
> +
> + __asm__ __volatile__ (
> + "rdtime.d %[cycles], $zero\n"
> + : [cycles] "=r" (count)
> + ::
> + );
> + return count;
> +}
> +
> +/**
> + * Read the time base register.
> + *
> + * @return
> + * The time base for this lcore.
> + */
> +static inline uint64_t
> +rte_rdtsc(void)
> +{
> + return get_cycle_count();
> +}
> +
> +static inline uint64_t
> +rte_rdtsc_precise(void)
> +{
> + rte_mb();
> + return rte_rdtsc();
> +}
> +
> +static inline uint64_t
> +rte_get_tsc_cycles(void) { return rte_rdtsc(); }
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* _RTE_CYCLES_LOONGARCH_H_ */
[snip]
> diff --git a/lib/eal/loongarch/rte_cpuflags.c b/lib/eal/loongarch/rte_cpuflags.c
> new file mode 100644
> index 0000000000..4abcd0fdb3
> --- /dev/null
> +++ b/lib/eal/loongarch/rte_cpuflags.c
> @@ -0,0 +1,94 @@
> +/*
> + * SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Loongson Technology Corporation Limited
> + */
> +
> +#include "rte_cpuflags.h"
> +
> +#include <elf.h>
> +#include <fcntl.h>
> +#include <assert.h>
> +#include <unistd.h>
> +#include <string.h>
> +
> +/* Symbolic values for the entries in the auxiliary table */
> +#define AT_HWCAP 16
> +#define AT_HWCAP2 26
AT_HWCAP2 is not used.
> +
> +/* software based registers */
> +enum cpu_register_t {
> + REG_NONE = 0,
> + REG_HWCAP,
> + REG_MAX
> +};
> +
> +typedef uint32_t hwcap_registers_t[REG_MAX];
> +
> +struct feature_entry {
> + uint32_t reg;
> + uint32_t bit;
> +#define CPU_FLAG_NAME_MAX_LEN 64
> + char name[CPU_FLAG_NAME_MAX_LEN];
> +};
> +
> +#define FEAT_DEF(name, reg, bit) \
> + [RTE_CPUFLAG_##name] = {reg, bit, #name},
> +
> +const struct feature_entry rte_cpu_feature_table[] = {
> + FEAT_DEF(CPUCFG, REG_HWCAP, 0)
> + FEAT_DEF(LAM, REG_HWCAP, 1)
> + FEAT_DEF(UAL, REG_HWCAP, 2)
> + FEAT_DEF(FPU, REG_HWCAP, 3)
> + FEAT_DEF(LSX, REG_HWCAP, 4)
> + FEAT_DEF(LASX, REG_HWCAP, 5)
> + FEAT_DEF(CRC32, REG_HWCAP, 6)
> + FEAT_DEF(COMPLEX, REG_HWCAP, 7)
> + FEAT_DEF(CRYPTO, REG_HWCAP, 8)
> + FEAT_DEF(LVZ, REG_HWCAP, 9)
> + FEAT_DEF(LBT_X86, REG_HWCAP, 10)
> + FEAT_DEF(LBT_ARM, REG_HWCAP, 11)
> + FEAT_DEF(LBT_MIPS, REG_HWCAP, 12)
> +};
> +
> +/*
> + * Read AUXV software register and get cpu features for LoongArch
> + */
> +static void
> +rte_cpu_get_features(hwcap_registers_t out)
> +{
> + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
> +}
> +
> +/*
> + * Checks if a particular flag is available on current machine.
> + */
> +int
> +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
> +{
> + const struct feature_entry *feat;
> + hwcap_registers_t regs = {0};
> +
> + if (feature >= RTE_CPUFLAG_NUMFLAGS)
> + return -ENOENT;
> +
> + feat = &rte_cpu_feature_table[feature];
> + if (feat->reg == REG_NONE)
> + return -EFAULT;
> +
> + rte_cpu_get_features(regs);
> + return (regs[feat->reg] >> feat->bit) & 1;
> +}
> +
> +const char *
> +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
> +{
> + if (feature >= RTE_CPUFLAG_NUMFLAGS)
> + return NULL;
> + return rte_cpu_feature_table[feature].name;
> +}
> +
> +void
> +rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
> +{
> + memset(intrinsics, 0, sizeof(*intrinsics));
> +}
[snip]
On Thu, Aug 25, 2022 at 3:56 PM David Marchand
<david.marchand@redhat.com> wrote:
>
> This is only a first pass.
Additionnally, please run ./devtools/check-meson.py.
I see tabulations where we expect spaces.
Hi David,
I appreciate you giving me these helpful comments.
On Thu, Aug 25, 2022 at 21:56, David Marchand wrote:
> This is only a first pass.
>
> On Wed, Aug 24, 2022 at 10:31 AM Min Zhou <zhoumin@loongson.cn> wrote:
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 32ffdd1a61..f00b82b5ce 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -311,6 +311,12 @@ F: config/riscv/
>> F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
>> F: lib/eal/riscv/
>>
>> +LoongArch
>> +M: Min Zhou <zhoumin@loongson.cn>
>> +F: config/loongarch/
>> +F: doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
>> +F: lib/eal/loongarch/
>> +
> I tried to put entries in MAINTAINERS in a pseudo alphabetical order
> (ignoring the vendor name).
> We currently have: ARM, Power, RISC-V, X86.
>
> As a consequence, the block for LoongArch should be moved between ARM,
> and Power arches.
OK, thanks. I will place the block for LoongArch at the appropriate
location.
>
>> Intel x86
>> M: Bruce Richardson <bruce.richardson@intel.com>
>> M: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
> [snip]
>
>> diff --git a/config/loongarch/meson.build b/config/loongarch/meson.build
>> new file mode 100644
>> index 0000000000..e052fbad7f
>> --- /dev/null
>> +++ b/config/loongarch/meson.build
>> @@ -0,0 +1,43 @@
>> +# SPDX-License-Identifier: BSD-3-Clause
>> +# Copyright(c) 2022 Loongson Technology Corporation Limited
>> +
>> +if not dpdk_conf.get('RTE_ARCH_64')
>> + error('Only 64-bit compiles are supported for this platform type')
>> +endif
>> +dpdk_conf.set('RTE_ARCH', 'loongarch')
>> +dpdk_conf.set('RTE_ARCH_LOONGARCH', 1)
>> +dpdk_conf.set('RTE_ARCH_NO_VECTOR', 1)
> ?
> RTE_ARCH_NO_VECTOR is not used anywhere, please remove.
OK, thanks. I will remove it. This macro was applied to the patch set's
earlier iteration. I had already changed a few things to implement no vector
support, but I neglected to get rid of this definition.
>
>> +
>> +machine_args_generic = [
>> + ['default', ['-march=loongarch64']],
>> +]
>> +
>> +flags_generic = [
>> + ['RTE_MACHINE', '"loongarch64"'],
>> + ['RTE_MAX_LCORE', 64],
>> + ['RTE_MAX_NUMA_NODES', 16],
>> + ['RTE_CACHE_LINE_SIZE', 64]]
>> +
>> +impl_generic = ['Generic loongarch', flags_generic, machine_args_generic]
>> +
>> +machine = []
>> +machine_args = []
>> +
>> +machine = impl_generic
>> +impl_pn = 'default'
>> +
>> +message('Implementer : ' + machine[0])
>> +foreach flag: machine[1]
>> + if flag.length() > 0
>> + dpdk_conf.set(flag[0], flag[1])
>> + endif
>> +endforeach
>> +
>> +foreach marg: machine[2]
>> + if marg[0] == impl_pn
>> + foreach f: marg[1]
>> + machine_args += f
>> + endforeach
>> + endif
>> +endforeach
>> +message(machine_args)
> [snip]
>
>> diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst
>> index 747552c385..c34966b241 100644
>> --- a/doc/guides/linux_gsg/index.rst
>> +++ b/doc/guides/linux_gsg/index.rst
>> @@ -15,6 +15,7 @@ Getting Started Guide for Linux
>> build_dpdk
>> cross_build_dpdk_for_arm64
>> cross_build_dpdk_for_riscv
>> + cross_build_dpdk_for_loongarch
> In alphabetical order please.
OK, thanks. I will change it.
>
>> linux_drivers
>> build_sample_apps
>> linux_eal_parameters
>> diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst
>> index 7f6cb914a5..8afa7ef7fd 100644
>> --- a/doc/guides/nics/features.rst
>> +++ b/doc/guides/nics/features.rst
>> @@ -848,6 +848,12 @@ rv64
>> Support 64-bit RISC-V architecture.
>>
>>
>> +LoongArch64
>> +-----------
>> +
>> +Support 64-bit LoongArch architecture.
>> +
>> +
> Idem.
OK, thanks. I will change it.
>
>> x86-32
>> ------
>>
>> diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini
>> index d1db0c256a..8bbc4600bd 100644
>> --- a/doc/guides/nics/features/default.ini
>> +++ b/doc/guides/nics/features/default.ini
>> @@ -73,6 +73,7 @@ ARMv7 =
>> ARMv8 =
>> Power8 =
>> rv64 =
>> +LoongArch64 =
> Idem.
OK, thanks. I will change it.
>
>> x86-32 =
>> x86-64 =
>> Usage doc =
>> diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst
>> index 8c021cf050..126160d683 100644
>> --- a/doc/guides/rel_notes/release_22_11.rst
>> +++ b/doc/guides/rel_notes/release_22_11.rst
>> @@ -55,6 +55,12 @@ New Features
>> Also, make sure to start the actual text at the margin.
>> =======================================================
>>
>> +* **Added initial LoongArch architecture support.**
>> +
>> + Added EAL implementation for LoongArch architecture. The initial devices
>> + the porting was tested on included Loongson 3A5000, Loongson 3C5000 and
>> + Loongson 3C5000L. In theory this implementation should work with any target
>> + based on ``LoongArch`` ISA.
> Sections in the release notes are separated with two empty lines.
OK, thanks. I will put an empty line once more above the subsequent part.
>> Removed Items
>> -------------
> [snip]
>
>> diff --git a/lib/eal/loongarch/include/meson.build b/lib/eal/loongarch/include/meson.build
>> new file mode 100644
>> index 0000000000..d5699c5373
>> --- /dev/null
>> +++ b/lib/eal/loongarch/include/meson.build
>> @@ -0,0 +1,21 @@
>> +# SPDX-License-Identifier: BSD-3-Clause
>> +# Copyright(c) 2022 Loongson Technology Corporation Limited
>> +
>> +arch_headers = files(
>> + 'rte_atomic.h',
>> + 'rte_byteorder.h',
>> + 'rte_cpuflags.h',
>> + 'rte_cycles.h',
>> + 'rte_io.h',
>> + 'rte_mcslock.h',
>> + 'rte_memcpy.h',
>> + 'rte_pause.h',
>> + 'rte_pflock.h',
>> + 'rte_power_intrinsics.h',
>> + 'rte_prefetch.h',
>> + 'rte_rwlock.h',
>> + 'rte_spinlock.h',
>> + 'rte_ticketlock.h',
>> + 'rte_vect.h',
>> +)
> msclock, pflock and ticketlock are now non-arch specific headers.
> They can be removed from the loongarch include directory.
> See: e5e613f05b8c ("eal: remove unused arch-specific headers for locks")
OK, thanks. I will remove these files.
>
>> +install_headers(arch_headers, subdir: get_option('include_subdir_arch'))
>> diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h
>> new file mode 100644
>> index 0000000000..8e007e7f76
>> --- /dev/null
>> +++ b/lib/eal/loongarch/include/rte_atomic.h
>> @@ -0,0 +1,253 @@
>> +/* SPDX-License-Identifier: BSD-3-Clause
>> + * Copyright(c) 2022 Loongson Technology Corporation Limited
>> + */
>> +
>> +#ifndef _RTE_ATOMIC_LOONGARCH_H_
>> +#define _RTE_ATOMIC_LOONGARCH_H_
>> +
>> +#ifdef __cplusplus
>> +extern "C" {
>> +#endif
>> +
>> +#include <stdint.h>
>> +#include "generic/rte_atomic.h"
>> +
>> +/**
>> + * LoongArch Synchronize
>> + */
>> +static inline void synchronize(void)
> This name is too generic.
> Plus all memory barriers are implemented in the same way.
>
> I suggest defining rte_mb() as this inline helper.
OK, thanks. I will change it as you suggest.
>
>> +{
>> + __asm__ __volatile__("dbar 0":::"memory");
>> +}
>> +
>> +/**
>> + * General memory barrier.
>> + *
>> + * Guarantees that the LOAD and STORE operations generated before the
>> + * barrier occur before the LOAD and STORE operations generated after.
>> + * This function is architecture dependent.
> Those comments are copied from the generic header which is used for
> doxygen, but you don't need them in the arch specific header.
> Please remove.
OK, thanks. I will remove those comments.
>> + */
>> +#define rte_mb() synchronize()
>> +
>> +/**
>> + * Write memory barrier.
>> + *
>> + * Guarantees that the STORE operations generated before the barrier
>> + * occur before the STORE operations generated after.
>> + * This function is architecture dependent.
>> + */
>> +#define rte_wmb() synchronize()
>> +
>> +/**
>> + * Read memory barrier.
>> + *
>> + * Guarantees that the LOAD operations generated before the barrier
>> + * occur before the LOAD operations generated after.
>> + * This function is architecture dependent.
>> + */
>> +#define rte_rmb() synchronize()
>> +
>> +#define rte_smp_mb() rte_mb()
>> +
>> +#define rte_smp_wmb() rte_mb()
>> +
>> +#define rte_smp_rmb() rte_mb()
>> +
>> +#define rte_io_mb() rte_mb()
>> +
>> +#define rte_io_wmb() rte_mb()
>> +
>> +#define rte_io_rmb() rte_mb()
>> +
>> +static __rte_always_inline void
>> +rte_atomic_thread_fence(int memorder)
>> +{
>> + __atomic_thread_fence(memorder);
>> +}
>> +
>> +#ifndef RTE_FORCE_INTRINSICS
> Unless I missed something, there is no loongarch specific
> implementations when RTE_FORCE_INTRINSICS is unset.
> What is the point of supporting the case where RTE_FORCE_INTRINSICS is
> undefined?
>
> If there is no need, force-set RTE_FORCE_INTRINSICS in config and then
> update headers accordingly.
OK, thanks. In fact, there are no implementations specifically for LoongArch
when RTE_FORCE_INTRINSICS is undefined. I will force-set
RTE_FORCE_INTRINSICS
in config and include generic implementations for LoongArch.
>
>> +/*------------------------- 16 bit atomic operations -------------------------*/
>> +static inline int
>> +rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
>> +{
>> + return __sync_bool_compare_and_swap(dst, exp, src);
>> +}
>> +
>> +static inline uint16_t
>> +rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
>> +{
>> +#if defined(__clang__)
>> + return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);
>> +#else
>> + return __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST);
>> +#endif
>> +}
>> +
>> +static inline void
>> +rte_atomic16_inc(rte_atomic16_t *v)
>> +{
>> + rte_atomic16_add(v, 1);
>> +}
>> +
>> +static inline void
>> +rte_atomic16_dec(rte_atomic16_t *v)
>> +{
>> + rte_atomic16_sub(v, 1);
>> +}
>> +
>> +static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
>> +{
>> + return __sync_add_and_fetch(&v->cnt, 1) == 0;
>> +}
>> +
>> +static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
>> +{
>> + return __sync_sub_and_fetch(&v->cnt, 1) == 0;
>> +}
>> +
>> +static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
>> +{
>> + return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
>> +}
>> +
>> +/*------------------------- 32 bit atomic operations -------------------------*/
>> +static inline int
>> +rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
>> +{
>> + return __sync_bool_compare_and_swap(dst, exp, src);
>> +}
>> +
>> +static inline uint32_t
>> +rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
>> +{
>> +#if defined(__clang__)
>> + return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);
>> +#else
>> + return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST);
>> +#endif
>> +}
>> +
>> +static inline void
>> +rte_atomic32_inc(rte_atomic32_t *v)
>> +{
>> + rte_atomic32_add(v, 1);
>> +}
>> +
>> +static inline void
>> +rte_atomic32_dec(rte_atomic32_t *v)
>> +{
>> + rte_atomic32_sub(v, 1);
>> +}
>> +
>> +static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
>> +{
>> + return __sync_add_and_fetch(&v->cnt, 1) == 0;
>> +}
>> +
>> +static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
>> +{
>> + return __sync_sub_and_fetch(&v->cnt, 1) == 0;
>> +}
>> +
>> +static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
>> +{
>> + return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
>> +}
>> +
>> +/*------------------------- 64 bit atomic operations -------------------------*/
>> +static inline int
>> +rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
>> +{
>> + return __sync_bool_compare_and_swap(dst, exp, src);
>> +}
>> +
>> +static inline uint64_t
>> +rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
>> +{
>> +#if defined(__clang__)
>> + return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);
>> +#else
>> + return __atomic_exchange_8(dst, val, __ATOMIC_SEQ_CST);
>> +#endif
>> +}
>> +
>> +static inline void
>> +rte_atomic64_init(rte_atomic64_t *v)
>> +{
>> + v->cnt = 0;
>> +}
>> +
>> +static inline int64_t
>> +rte_atomic64_read(rte_atomic64_t *v)
>> +{
>> + return v->cnt;
>> +}
>> +
>> +static inline void
>> +rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
>> +{
>> + v->cnt = new_value;
>> +}
>> +
>> +static inline void
>> +rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
>> +{
>> + __sync_fetch_and_add(&v->cnt, inc);
>> +}
>> +
>> +static inline void
>> +rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
>> +{
>> + __sync_fetch_and_sub(&v->cnt, dec);
>> +}
>> +
>> +static inline void
>> +rte_atomic64_inc(rte_atomic64_t *v)
>> +{
>> + rte_atomic64_add(v, 1);
>> +}
>> +
>> +static inline void
>> +rte_atomic64_dec(rte_atomic64_t *v)
>> +{
>> + rte_atomic64_sub(v, 1);
>> +}
>> +
>> +static inline int64_t
>> +rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
>> +{
>> + return __sync_add_and_fetch(&v->cnt, inc);
>> +}
>> +
>> +static inline int64_t
>> +rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
>> +{
>> + return __sync_sub_and_fetch(&v->cnt, dec);
>> +}
>> +
>> +static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
>> +{
>> + return rte_atomic64_add_return(v, 1) == 0;
>> +}
>> +
>> +static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
>> +{
>> + return rte_atomic64_sub_return(v, 1) == 0;
>> +}
>> +
>> +static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
>> +{
>> + return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
>> +}
>> +
>> +static inline void rte_atomic64_clear(rte_atomic64_t *v)
>> +{
>> + rte_atomic64_set(v, 0);
>> +}
>> +#endif
>> +
>> +#ifdef __cplusplus
>> +}
>> +#endif
>> +
>> +#endif /* _RTE_ATOMIC_LOONGARCH_H_ */
> [snip]
>
>> diff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h
>> new file mode 100644
>> index 0000000000..1f8f957faf
>> --- /dev/null
>> +++ b/lib/eal/loongarch/include/rte_cycles.h
>> @@ -0,0 +1,53 @@
>> +/* SPDX-License-Identifier: BSD-3-Clause
>> + * Copyright(c) 2022 Loongson Technology Corporation Limited
>> + */
>> +
>> +#ifndef _RTE_CYCLES_LOONGARCH_H_
>> +#define _RTE_CYCLES_LOONGARCH_H_
>> +
>> +#ifdef __cplusplus
>> +extern "C" {
>> +#endif
>> +
>> +#include "generic/rte_cycles.h"
>> +
>> +static inline uint64_t
>> +get_cycle_count(void)
> Same comment as earlier for memory barriers, this name is too generic.
> Prefer rte_rdtsc() as the name for this helper.
OK, thanks. I will change it as you suggest.
>
>> +{
>> + uint64_t count;
>> +
>> + __asm__ __volatile__ (
>> + "rdtime.d %[cycles], $zero\n"
>> + : [cycles] "=r" (count)
>> + ::
>> + );
>> + return count;
>> +}
>> +
>> +/**
>> + * Read the time base register.
>> + *
>> + * @return
>> + * The time base for this lcore.
>> + */
>> +static inline uint64_t
>> +rte_rdtsc(void)
>> +{
>> + return get_cycle_count();
>> +}
>> +
>> +static inline uint64_t
>> +rte_rdtsc_precise(void)
>> +{
>> + rte_mb();
>> + return rte_rdtsc();
>> +}
>> +
>> +static inline uint64_t
>> +rte_get_tsc_cycles(void) { return rte_rdtsc(); }
>> +
>> +#ifdef __cplusplus
>> +}
>> +#endif
>> +
>> +#endif /* _RTE_CYCLES_LOONGARCH_H_ */
> [snip]
>
>> diff --git a/lib/eal/loongarch/rte_cpuflags.c b/lib/eal/loongarch/rte_cpuflags.c
>> new file mode 100644
>> index 0000000000..4abcd0fdb3
>> --- /dev/null
>> +++ b/lib/eal/loongarch/rte_cpuflags.c
>> @@ -0,0 +1,94 @@
>> +/*
>> + * SPDX-License-Identifier: BSD-3-Clause
>> + * Copyright(c) 2022 Loongson Technology Corporation Limited
>> + */
>> +
>> +#include "rte_cpuflags.h"
>> +
>> +#include <elf.h>
>> +#include <fcntl.h>
>> +#include <assert.h>
>> +#include <unistd.h>
>> +#include <string.h>
>> +
>> +/* Symbolic values for the entries in the auxiliary table */
>> +#define AT_HWCAP 16
>> +#define AT_HWCAP2 26
> AT_HWCAP2 is not used.
OK, thanks. I will remove it.
>
>> +
>> +/* software based registers */
>> +enum cpu_register_t {
>> + REG_NONE = 0,
>> + REG_HWCAP,
>> + REG_MAX
>> +};
>> +
>> +typedef uint32_t hwcap_registers_t[REG_MAX];
>> +
>> +struct feature_entry {
>> + uint32_t reg;
>> + uint32_t bit;
>> +#define CPU_FLAG_NAME_MAX_LEN 64
>> + char name[CPU_FLAG_NAME_MAX_LEN];
>> +};
>> +
>> +#define FEAT_DEF(name, reg, bit) \
>> + [RTE_CPUFLAG_##name] = {reg, bit, #name},
>> +
>> +const struct feature_entry rte_cpu_feature_table[] = {
>> + FEAT_DEF(CPUCFG, REG_HWCAP, 0)
>> + FEAT_DEF(LAM, REG_HWCAP, 1)
>> + FEAT_DEF(UAL, REG_HWCAP, 2)
>> + FEAT_DEF(FPU, REG_HWCAP, 3)
>> + FEAT_DEF(LSX, REG_HWCAP, 4)
>> + FEAT_DEF(LASX, REG_HWCAP, 5)
>> + FEAT_DEF(CRC32, REG_HWCAP, 6)
>> + FEAT_DEF(COMPLEX, REG_HWCAP, 7)
>> + FEAT_DEF(CRYPTO, REG_HWCAP, 8)
>> + FEAT_DEF(LVZ, REG_HWCAP, 9)
>> + FEAT_DEF(LBT_X86, REG_HWCAP, 10)
>> + FEAT_DEF(LBT_ARM, REG_HWCAP, 11)
>> + FEAT_DEF(LBT_MIPS, REG_HWCAP, 12)
>> +};
>> +
>> +/*
>> + * Read AUXV software register and get cpu features for LoongArch
>> + */
>> +static void
>> +rte_cpu_get_features(hwcap_registers_t out)
>> +{
>> + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
>> +}
>> +
>> +/*
>> + * Checks if a particular flag is available on current machine.
>> + */
>> +int
>> +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
>> +{
>> + const struct feature_entry *feat;
>> + hwcap_registers_t regs = {0};
>> +
>> + if (feature >= RTE_CPUFLAG_NUMFLAGS)
>> + return -ENOENT;
>> +
>> + feat = &rte_cpu_feature_table[feature];
>> + if (feat->reg == REG_NONE)
>> + return -EFAULT;
>> +
>> + rte_cpu_get_features(regs);
>> + return (regs[feat->reg] >> feat->bit) & 1;
>> +}
>> +
>> +const char *
>> +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
>> +{
>> + if (feature >= RTE_CPUFLAG_NUMFLAGS)
>> + return NULL;
>> + return rte_cpu_feature_table[feature].name;
>> +}
>> +
>> +void
>> +rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
>> +{
>> + memset(intrinsics, 0, sizeof(*intrinsics));
>> +}
> [snip]
>
>
Thanks,
Min Zhou
Hi David,
Thank you very much for your reminder.
On Thu, Aug 25, 2022 at 22:04, David Marchand wrote:
> On Thu, Aug 25, 2022 at 3:56 PM David Marchand
> <david.marchand@redhat.com> wrote:
>> This is only a first pass.
> Additionnally, please run ./devtools/check-meson.py.
> I see tabulations where we expect spaces.
OK, thanks. I just became aware of these errors that this
tool has reported. I will fix them.
--
Thanks,
Min Zhou
@@ -311,6 +311,12 @@ F: config/riscv/
F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
F: lib/eal/riscv/
+LoongArch
+M: Min Zhou <zhoumin@loongson.cn>
+F: config/loongarch/
+F: doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
+F: lib/eal/loongarch/
+
Intel x86
M: Bruce Richardson <bruce.richardson@intel.com>
M: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
@@ -65,6 +65,18 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
return data;
}
+#elif defined(RTE_ARCH_LOONGARCH)
+
+#define vect_loadu_sil128(p) vect_load_128(p)
+
+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
+static __rte_always_inline xmm_t
+vect_set_epi32(int i3, int i2, int i1, int i0)
+{
+ xmm_t data = (xmm_t){.u32 = {i0, i1, i2, i3}};
+
+ return data;
+}
#endif
#endif /* _TEST_XMMT_OPS_H_ */
new file mode 100644
@@ -0,0 +1,16 @@
+[binaries]
+c = 'loongarch64-unknown-linux-gnu-gcc'
+cpp = 'loongarch64-unknown-linux-gnu-cpp'
+ar = 'loongarch64-unknown-linux-gnu-gcc-ar'
+strip = 'loongarch64-unknown-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'loongarch64'
+cpu = '3a5000'
+endian = 'little'
+
+[properties]
+implementor_id = 'generic'
+implementor_pn = 'default'
new file mode 100644
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2022 Loongson Technology Corporation Limited
+
+if not dpdk_conf.get('RTE_ARCH_64')
+ error('Only 64-bit compiles are supported for this platform type')
+endif
+dpdk_conf.set('RTE_ARCH', 'loongarch')
+dpdk_conf.set('RTE_ARCH_LOONGARCH', 1)
+dpdk_conf.set('RTE_ARCH_NO_VECTOR', 1)
+
+machine_args_generic = [
+ ['default', ['-march=loongarch64']],
+]
+
+flags_generic = [
+ ['RTE_MACHINE', '"loongarch64"'],
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 16],
+ ['RTE_CACHE_LINE_SIZE', 64]]
+
+impl_generic = ['Generic loongarch', flags_generic, machine_args_generic]
+
+machine = []
+machine_args = []
+
+machine = impl_generic
+impl_pn = 'default'
+
+message('Implementer : ' + machine[0])
+foreach flag: machine[1]
+ if flag.length() > 0
+ dpdk_conf.set(flag[0], flag[1])
+ endif
+endforeach
+
+foreach marg: machine[2]
+ if marg[0] == impl_pn
+ foreach f: marg[1]
+ machine_args += f
+ endforeach
+ endif
+endforeach
+message(machine_args)
@@ -42,7 +42,7 @@ Per Architecture Sources
The following macro options can be used:
* ``RTE_ARCH`` is a string that contains the name of the architecture.
-* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
+* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_LOONGARCH``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
Per Execution Environment Sources
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
new file mode 100644
@@ -0,0 +1,87 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2022 Loongson Technology Corporation Limited
+
+Cross compiling DPDK for LoongArch
+==================================
+
+This chapter describes how to cross compile DPDK for LoongArch from x86 build
+hosts.
+
+.. note::
+
+ Due to some of the code under review, the current Linux 5.19 cannot boot
+ on LoongArch system. There are still some Linux distributions that have
+ supported LoongArch host, such as Anolis OS, Kylin, Loongnix and UOS. These
+ distributions base on Linux kernel 4.19 supported by Loongson Corporation.
+ Because LoongArch is such a new platform with many fundamental pieces of
+ software still under development, it is currently recommended to cross
+ compile DPDK on x86 for LoongArch.
+
+
+Prerequisites
+-------------
+
+Ensure that you have all pre-requisites for building DPDK natively as those
+will be required also for cross-compilation.
+
+Linux kernel
+~~~~~~~~~~~~
+
+Make sure that LoongArch host is running Linux kernel 4.19 or newer supported
+by Loongson Corporation. The support for LoongArch in the current Linux 5.19
+is not complete because it still misses some patches to add for other
+subsystems.
+
+GNU toolchain
+-------------
+
+Obtain the cross toolchain
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The build process was tested using:
+
+* Latest `LoongArch GNU toolchain
+ <https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz>`_
+ on Debian 10.4 or CentOS 8.
+
+Alternatively the toolchain may be built straight from the source via CLFS, to
+do that follow the instructions on `CLFS for LoongArch64
+<https://github.com/sunhaiyong1978/CLFS-for-LoongArch>`_ github page.
+
+To download cross tools from github we can use the following command:
+
+.. code-block:: console
+
+ wget -P /tmp/ https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz
+
+Unzip and add into the PATH
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+After downloading the cross-tools file, we need unzip and add those executable
+binaries into the PATH as follows:
+
+.. code-block:: console
+
+ tar -xvf /tmp/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz -C <cross_tool_install_dir> --strip-components 1
+ export PATH=$PATH:<cross_tool_install_dir>/bin
+
+
+Cross Compiling DPDK with GNU toolchain using Meson
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To cross-compile DPDK for generic LoongArch we can use the following command:
+
+.. code-block:: console
+
+ meson cross-build --cross-file config/loongarch/loongarch_loongarch64_linux_gcc
+ ninja -C cross-build
+
+Supported cross-compilation targets
+-----------------------------------
+
+Currently the following target is supported:
+
+* Generic LoongArch64 ISA: ``config/loongarch/loongarch_loongarch64_linux_gcc``
+
+To add a new target support, a corresponding cross-file has to be added to
+``config/loongarch`` directory.
@@ -15,6 +15,7 @@ Getting Started Guide for Linux
build_dpdk
cross_build_dpdk_for_arm64
cross_build_dpdk_for_riscv
+ cross_build_dpdk_for_loongarch
linux_drivers
build_sample_apps
linux_eal_parameters
@@ -848,6 +848,12 @@ rv64
Support 64-bit RISC-V architecture.
+LoongArch64
+-----------
+
+Support 64-bit LoongArch architecture.
+
+
x86-32
------
@@ -73,6 +73,7 @@ ARMv7 =
ARMv8 =
Power8 =
rv64 =
+LoongArch64 =
x86-32 =
x86-64 =
Usage doc =
@@ -55,6 +55,12 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Added initial LoongArch architecture support.**
+
+ Added EAL implementation for LoongArch architecture. The initial devices
+ the porting was tested on included Loongson 3A5000, Loongson 3C5000 and
+ Loongson 3C5000L. In theory this implementation should work with any target
+ based on ``LoongArch`` ISA.
Removed Items
-------------
@@ -7,6 +7,12 @@ if arch_subdir == 'riscv'
subdir_done()
endif
+if arch_subdir == 'loongarch'
+ build = false
+ reason = 'not supported on LoongArch'
+ subdir_done()
+endif
+
cflags += ['-DPF_DRIVER',
'-DVF_DRIVER',
'-DINTEGRATED_VF',
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
+if arch_subdir == 'loongarch'
+ build = false
+ reason = 'not supported on LoongArch'
+ subdir_done()
+endif
+
cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
subdir('base')
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright 2018-2019 Cisco Systems, Inc. All rights reserved.
+if arch_subdir == 'loongarch'
+ build = false
+ reason = 'not supported on LoongArch'
+ subdir_done()
+endif
+
if not is_linux
build = false
reason = 'only supported on Linux'
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright 2018 Luca Boccassi <bluca@debian.org>
+if arch_subdir == 'loongarch'
+ build = false
+ reason = 'not supported on LoongArch'
+ subdir_done()
+endif
+
if not is_linux
build = false
reason = 'only supported on Linux'
@@ -6,6 +6,12 @@
# To build this example as a standalone application with an already-installed
# DPDK instance, use 'make'
+if arch_subdir == 'loongarch'
+ build = false
+ reason = 'not supported on LoongArch'
+ subdir_done()
+endif
+
allow_experimental_apis = true
deps += ['acl', 'hash', 'lpm', 'fib', 'eventdev']
sources = files(
@@ -77,7 +77,11 @@ uint64_t eal_get_baseaddr(void)
* rte_mem_check_dma_mask for ensuring all memory is within supported
* range.
*/
+#if defined(RTE_ARCH_LOONGARCH)
+ return 0x7000000000ULL;
+#else
return 0x100000000ULL;
+#endif
}
/*
new file mode 100644
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2022 Loongson Technology Corporation Limited
+
+arch_headers = files(
+ 'rte_atomic.h',
+ 'rte_byteorder.h',
+ 'rte_cpuflags.h',
+ 'rte_cycles.h',
+ 'rte_io.h',
+ 'rte_mcslock.h',
+ 'rte_memcpy.h',
+ 'rte_pause.h',
+ 'rte_pflock.h',
+ 'rte_power_intrinsics.h',
+ 'rte_prefetch.h',
+ 'rte_rwlock.h',
+ 'rte_spinlock.h',
+ 'rte_ticketlock.h',
+ 'rte_vect.h',
+)
+install_headers(arch_headers, subdir: get_option('include_subdir_arch'))
new file mode 100644
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_ATOMIC_LOONGARCH_H_
+#define _RTE_ATOMIC_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "generic/rte_atomic.h"
+
+/**
+ * LoongArch Synchronize
+ */
+static inline void synchronize(void)
+{
+ __asm__ __volatile__("dbar 0":::"memory");
+}
+
+/**
+ * General memory barrier.
+ *
+ * Guarantees that the LOAD and STORE operations generated before the
+ * barrier occur before the LOAD and STORE operations generated after.
+ * This function is architecture dependent.
+ */
+#define rte_mb() synchronize()
+
+/**
+ * Write memory barrier.
+ *
+ * Guarantees that the STORE operations generated before the barrier
+ * occur before the STORE operations generated after.
+ * This function is architecture dependent.
+ */
+#define rte_wmb() synchronize()
+
+/**
+ * Read memory barrier.
+ *
+ * Guarantees that the LOAD operations generated before the barrier
+ * occur before the LOAD operations generated after.
+ * This function is architecture dependent.
+ */
+#define rte_rmb() synchronize()
+
+#define rte_smp_mb() rte_mb()
+
+#define rte_smp_wmb() rte_mb()
+
+#define rte_smp_rmb() rte_mb()
+
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_mb()
+
+#define rte_io_rmb() rte_mb()
+
+static __rte_always_inline void
+rte_atomic_thread_fence(int memorder)
+{
+ __atomic_thread_fence(memorder);
+}
+
+#ifndef RTE_FORCE_INTRINSICS
+/*------------------------- 16 bit atomic operations -------------------------*/
+static inline int
+rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
+{
+ return __sync_bool_compare_and_swap(dst, exp, src);
+}
+
+static inline uint16_t
+rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
+{
+#if defined(__clang__)
+ return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);
+#else
+ return __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST);
+#endif
+}
+
+static inline void
+rte_atomic16_inc(rte_atomic16_t *v)
+{
+ rte_atomic16_add(v, 1);
+}
+
+static inline void
+rte_atomic16_dec(rte_atomic16_t *v)
+{
+ rte_atomic16_sub(v, 1);
+}
+
+static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
+{
+ return __sync_add_and_fetch(&v->cnt, 1) == 0;
+}
+
+static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
+{
+ return __sync_sub_and_fetch(&v->cnt, 1) == 0;
+}
+
+static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
+{
+ return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
+}
+
+/*------------------------- 32 bit atomic operations -------------------------*/
+static inline int
+rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
+{
+ return __sync_bool_compare_and_swap(dst, exp, src);
+}
+
+static inline uint32_t
+rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
+{
+#if defined(__clang__)
+ return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);
+#else
+ return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST);
+#endif
+}
+
+static inline void
+rte_atomic32_inc(rte_atomic32_t *v)
+{
+ rte_atomic32_add(v, 1);
+}
+
+static inline void
+rte_atomic32_dec(rte_atomic32_t *v)
+{
+ rte_atomic32_sub(v, 1);
+}
+
+static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
+{
+ return __sync_add_and_fetch(&v->cnt, 1) == 0;
+}
+
+static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
+{
+ return __sync_sub_and_fetch(&v->cnt, 1) == 0;
+}
+
+static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
+{
+ return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
+}
+
+/*------------------------- 64 bit atomic operations -------------------------*/
+static inline int
+rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
+{
+ return __sync_bool_compare_and_swap(dst, exp, src);
+}
+
+static inline uint64_t
+rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
+{
+#if defined(__clang__)
+ return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);
+#else
+ return __atomic_exchange_8(dst, val, __ATOMIC_SEQ_CST);
+#endif
+}
+
+static inline void
+rte_atomic64_init(rte_atomic64_t *v)
+{
+ v->cnt = 0;
+}
+
+static inline int64_t
+rte_atomic64_read(rte_atomic64_t *v)
+{
+ return v->cnt;
+}
+
+static inline void
+rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
+{
+ v->cnt = new_value;
+}
+
+static inline void
+rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
+{
+ __sync_fetch_and_add(&v->cnt, inc);
+}
+
+static inline void
+rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
+{
+ __sync_fetch_and_sub(&v->cnt, dec);
+}
+
+static inline void
+rte_atomic64_inc(rte_atomic64_t *v)
+{
+ rte_atomic64_add(v, 1);
+}
+
+static inline void
+rte_atomic64_dec(rte_atomic64_t *v)
+{
+ rte_atomic64_sub(v, 1);
+}
+
+static inline int64_t
+rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
+{
+ return __sync_add_and_fetch(&v->cnt, inc);
+}
+
+static inline int64_t
+rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
+{
+ return __sync_sub_and_fetch(&v->cnt, dec);
+}
+
+static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
+{
+ return rte_atomic64_add_return(v, 1) == 0;
+}
+
+static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
+{
+ return rte_atomic64_sub_return(v, 1) == 0;
+}
+
+static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
+{
+ return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
+}
+
+static inline void rte_atomic64_clear(rte_atomic64_t *v)
+{
+ rte_atomic64_set(v, 0);
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_ATOMIC_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_BYTEORDER_LOONGARCH_H_
+#define _RTE_BYTEORDER_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_byteorder.h"
+
+#ifndef RTE_FORCE_INTRINSICS
+#define rte_bswap16(x) rte_constant_bswap16(x)
+#define rte_bswap32(x) rte_constant_bswap32(x)
+#define rte_bswap64(x) rte_constant_bswap64(x)
+#endif
+
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+
+#define rte_cpu_to_le_16(x) (x)
+#define rte_cpu_to_le_32(x) (x)
+#define rte_cpu_to_le_64(x) (x)
+
+#define rte_cpu_to_be_16(x) rte_bswap16(x)
+#define rte_cpu_to_be_32(x) rte_bswap32(x)
+#define rte_cpu_to_be_64(x) rte_bswap64(x)
+
+#define rte_le_to_cpu_16(x) (x)
+#define rte_le_to_cpu_32(x) (x)
+#define rte_le_to_cpu_64(x) (x)
+
+#define rte_be_to_cpu_16(x) rte_bswap16(x)
+#define rte_be_to_cpu_32(x) rte_bswap32(x)
+#define rte_be_to_cpu_64(x) rte_bswap64(x)
+
+#else /* RTE_BIG_ENDIAN */
+#error "LoongArch not support big endian!"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_BYTEORDER_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_CPUFLAGS_LOONGARCH_H_
+#define _RTE_CPUFLAGS_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumeration of all CPU features supported
+ */
+enum rte_cpu_flag_t {
+ RTE_CPUFLAG_CPUCFG = 0,
+ RTE_CPUFLAG_LAM,
+ RTE_CPUFLAG_UAL,
+ RTE_CPUFLAG_FPU,
+ RTE_CPUFLAG_LSX,
+ RTE_CPUFLAG_LASX,
+ RTE_CPUFLAG_CRC32,
+ RTE_CPUFLAG_COMPLEX,
+ RTE_CPUFLAG_CRYPTO,
+ RTE_CPUFLAG_LVZ,
+ RTE_CPUFLAG_LBT_X86,
+ RTE_CPUFLAG_LBT_ARM,
+ RTE_CPUFLAG_LBT_MIPS,
+ /* The last item */
+ RTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */
+};
+
+#include "generic/rte_cpuflags.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CPUFLAGS_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_CYCLES_LOONGARCH_H_
+#define _RTE_CYCLES_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_cycles.h"
+
+static inline uint64_t
+get_cycle_count(void)
+{
+ uint64_t count;
+
+ __asm__ __volatile__ (
+ "rdtime.d %[cycles], $zero\n"
+ : [cycles] "=r" (count)
+ ::
+ );
+ return count;
+}
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ * The time base for this lcore.
+ */
+static inline uint64_t
+rte_rdtsc(void)
+{
+ return get_cycle_count();
+}
+
+static inline uint64_t
+rte_rdtsc_precise(void)
+{
+ rte_mb();
+ return rte_rdtsc();
+}
+
+static inline uint64_t
+rte_get_tsc_cycles(void) { return rte_rdtsc(); }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CYCLES_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_IO_LOONGARCH_H_
+#define _RTE_IO_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_io.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_IO_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_MCSLOCK_LOONGARCH_H_
+#define _RTE_MCSLOCK_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_mcslock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MCSLOCK_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_MEMCPY_LOONGARCH_H_
+#define _RTE_MEMCPY_LOONGARCH_H_
+
+#include <stdint.h>
+#include <string.h>
+
+#include "rte_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_memcpy.h"
+
+static inline void
+rte_mov16(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 16);
+}
+
+static inline void
+rte_mov32(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 32);
+}
+
+static inline void
+rte_mov48(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 48);
+}
+
+static inline void
+rte_mov64(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 64);
+}
+
+static inline void
+rte_mov128(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 128);
+}
+
+static inline void
+rte_mov256(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 256);
+}
+
+#define rte_memcpy(d, s, n) memcpy((d), (s), (n))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MEMCPY_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_PAUSE_LOONGARCH_H_
+#define _RTE_PAUSE_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "rte_atomic.h"
+
+#include "generic/rte_pause.h"
+
+static inline void rte_pause(void)
+{
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PAUSE_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+#ifndef _RTE_PFLOCK_LOONGARCH_H_
+#define _RTE_PFLOCK_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_pflock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PFLOCK_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_POWER_INTRINSIC_LOONGARCH_H_
+#define _RTE_POWER_INTRINSIC_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+
+#include "generic/rte_power_intrinsics.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_POWER_INTRINSIC_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_PREFETCH_LOONGARCH_H_
+#define _RTE_PREFETCH_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_prefetch.h"
+
+static inline void rte_prefetch0(const volatile void *p)
+{
+ __builtin_prefetch((const void *)(uintptr_t)p, 0, 3);
+}
+
+static inline void rte_prefetch1(const volatile void *p)
+{
+ __builtin_prefetch((const void *)(uintptr_t)p, 0, 2);
+}
+
+static inline void rte_prefetch2(const volatile void *p)
+{
+ __builtin_prefetch((const void *)(uintptr_t)p, 0, 1);
+}
+
+static inline void rte_prefetch_non_temporal(const volatile void *p)
+{
+ /* non-temporal version not available, fallback to rte_prefetch0 */
+ rte_prefetch0(p);
+}
+
+__rte_experimental
+static inline void
+rte_cldemote(const volatile void *p)
+{
+ RTE_SET_USED(p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PREFETCH_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_RWLOCK_LOONGARCH_H_
+#define _RTE_RWLOCK_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_rwlock.h"
+
+static inline void
+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_read_lock(rwl);
+}
+
+static inline void
+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_read_unlock(rwl);
+}
+
+static inline void
+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_write_lock(rwl);
+}
+
+static inline void
+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_write_unlock(rwl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_RWLOCK_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_SPINLOCK_LOONGARCH_H_
+#define _RTE_SPINLOCK_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_spinlock.h"
+
+#ifndef RTE_FORCE_INTRINSICS
+static inline void
+rte_spinlock_lock(rte_spinlock_t *sl)
+{
+ int exp = 0;
+
+ while (!__atomic_compare_exchange_n(&sl->locked, &exp, 1, 0,
+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {
+ rte_wait_until_equal_32((volatile uint32_t *)&sl->locked,
+ 0, __ATOMIC_RELAXED);
+ exp = 0;
+ }
+}
+
+static inline void
+rte_spinlock_unlock(rte_spinlock_t *sl)
+{
+ __atomic_store_n(&sl->locked, 0, __ATOMIC_RELEASE);
+}
+
+static inline int
+rte_spinlock_trylock(rte_spinlock_t *sl)
+{
+ int exp = 0;
+ return __atomic_compare_exchange_n(&sl->locked, &exp, 1,
+ 0, /* disallow spurious failure */
+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);
+}
+#endif
+
+static inline int rte_tm_supported(void)
+{
+ return 0;
+}
+
+static inline void
+rte_spinlock_lock_tm(rte_spinlock_t *sl)
+{
+ rte_spinlock_lock(sl); /* fall-back */
+}
+
+static inline int
+rte_spinlock_trylock_tm(rte_spinlock_t *sl)
+{
+ return rte_spinlock_trylock(sl);
+}
+
+static inline void
+rte_spinlock_unlock_tm(rte_spinlock_t *sl)
+{
+ rte_spinlock_unlock(sl);
+}
+
+static inline void
+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)
+{
+ rte_spinlock_recursive_lock(slr); /* fall-back */
+}
+
+static inline void
+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)
+{
+ rte_spinlock_recursive_unlock(slr);
+}
+
+static inline int
+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
+{
+ return rte_spinlock_recursive_trylock(slr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_SPINLOCK_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_TICKETLOCK_LOONGARCH_H_
+#define _RTE_TICKETLOCK_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_ticketlock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_TICKETLOCK_LOONGARCH_H_ */
new file mode 100644
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_VECT_LOONGARCH_H_
+#define _RTE_VECT_LOONGARCH_H_
+
+#include <stdint.h>
+#include "generic/rte_vect.h"
+#include "rte_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED
+
+typedef union xmm {
+ int8_t i8[16];
+ int16_t i16[8];
+ int32_t i32[4];
+ int64_t i64[2];
+ uint8_t u8[16];
+ uint16_t u16[8];
+ uint32_t u32[4];
+ uint64_t u64[2];
+ double pd[2];
+} __rte_aligned(16) xmm_t;
+
+#define XMM_SIZE (sizeof(xmm_t))
+#define XMM_MASK (XMM_SIZE - 1)
+
+typedef union rte_xmm {
+ xmm_t x;
+ uint8_t u8[XMM_SIZE / sizeof(uint8_t)];
+ uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
+ uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
+ uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
+ double pd[XMM_SIZE / sizeof(double)];
+} __rte_aligned(16) rte_xmm_t;
+
+static inline xmm_t
+vect_load_128(void *p)
+{
+ xmm_t ret = *((xmm_t *)p);
+
+ return ret;
+}
+
+static inline xmm_t
+vect_and(xmm_t data, xmm_t mask)
+{
+ rte_xmm_t ret = {.x = data };
+ rte_xmm_t m = {.x = mask };
+ ret.u64[0] &= m.u64[0];
+ ret.u64[1] &= m.u64[1];
+
+ return ret.x;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
new file mode 100644
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2022 Loongson Technology Corporation Limited
+
+subdir('include')
+
+sources += files(
+ 'rte_cpuflags.c',
+ 'rte_cycles.c',
+ 'rte_hypervisor.c',
+ 'rte_power_intrinsics.c',
+)
new file mode 100644
@@ -0,0 +1,94 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#include "rte_cpuflags.h"
+
+#include <elf.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <unistd.h>
+#include <string.h>
+
+/* Symbolic values for the entries in the auxiliary table */
+#define AT_HWCAP 16
+#define AT_HWCAP2 26
+
+/* software based registers */
+enum cpu_register_t {
+ REG_NONE = 0,
+ REG_HWCAP,
+ REG_MAX
+};
+
+typedef uint32_t hwcap_registers_t[REG_MAX];
+
+struct feature_entry {
+ uint32_t reg;
+ uint32_t bit;
+#define CPU_FLAG_NAME_MAX_LEN 64
+ char name[CPU_FLAG_NAME_MAX_LEN];
+};
+
+#define FEAT_DEF(name, reg, bit) \
+ [RTE_CPUFLAG_##name] = {reg, bit, #name},
+
+const struct feature_entry rte_cpu_feature_table[] = {
+ FEAT_DEF(CPUCFG, REG_HWCAP, 0)
+ FEAT_DEF(LAM, REG_HWCAP, 1)
+ FEAT_DEF(UAL, REG_HWCAP, 2)
+ FEAT_DEF(FPU, REG_HWCAP, 3)
+ FEAT_DEF(LSX, REG_HWCAP, 4)
+ FEAT_DEF(LASX, REG_HWCAP, 5)
+ FEAT_DEF(CRC32, REG_HWCAP, 6)
+ FEAT_DEF(COMPLEX, REG_HWCAP, 7)
+ FEAT_DEF(CRYPTO, REG_HWCAP, 8)
+ FEAT_DEF(LVZ, REG_HWCAP, 9)
+ FEAT_DEF(LBT_X86, REG_HWCAP, 10)
+ FEAT_DEF(LBT_ARM, REG_HWCAP, 11)
+ FEAT_DEF(LBT_MIPS, REG_HWCAP, 12)
+};
+
+/*
+ * Read AUXV software register and get cpu features for LoongArch
+ */
+static void
+rte_cpu_get_features(hwcap_registers_t out)
+{
+ out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
+}
+
+/*
+ * Checks if a particular flag is available on current machine.
+ */
+int
+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
+{
+ const struct feature_entry *feat;
+ hwcap_registers_t regs = {0};
+
+ if (feature >= RTE_CPUFLAG_NUMFLAGS)
+ return -ENOENT;
+
+ feat = &rte_cpu_feature_table[feature];
+ if (feat->reg == REG_NONE)
+ return -EFAULT;
+
+ rte_cpu_get_features(regs);
+ return (regs[feat->reg] >> feat->bit) & 1;
+}
+
+const char *
+rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
+{
+ if (feature >= RTE_CPUFLAG_NUMFLAGS)
+ return NULL;
+ return rte_cpu_feature_table[feature].name;
+}
+
+void
+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
+{
+ memset(intrinsics, 0, sizeof(*intrinsics));
+}
new file mode 100644
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#include "eal_private.h"
+
+#define LOONGARCH_CPUCFG4 0x4
+#define CPUCFG4_CCFREQ_MASK 0xFFFFFFFF
+#define CPUCFG4_CCFREQ_SHIFT 0
+
+#define LOONGARCH_CPUCFG5 0x5
+#define CPUCFG5_CCMUL_MASK 0xFFFF
+#define CPUCFG5_CCMUL_SHIFT 0
+
+#define CPUCFG5_CCDIV_MASK 0xFFFF0000
+#define CPUCFG5_CCDIV_SHIFT 16
+
+static __rte_noinline uint32_t
+read_cpucfg(int arg)
+{
+ int ret = 0;
+
+ __asm__ __volatile__ (
+ "cpucfg %[var], %[index]\n"
+ : [var]"=r"(ret)
+ : [index]"r"(arg)
+ :
+ );
+
+ return ret;
+}
+
+uint64_t
+get_tsc_freq_arch(void)
+{
+ uint32_t base_freq, mul_factor, div_factor;
+
+ base_freq = read_cpucfg(LOONGARCH_CPUCFG4);
+ mul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >>
+ CPUCFG5_CCMUL_SHIFT;
+ div_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >>
+ CPUCFG5_CCDIV_SHIFT;
+
+ return base_freq * mul_factor / div_factor;
+}
new file mode 100644
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#include "rte_hypervisor.h"
+
+enum rte_hypervisor
+rte_hypervisor_get(void)
+{
+ return RTE_HYPERVISOR_UNKNOWN;
+}
new file mode 100644
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#include "rte_power_intrinsics.h"
+
+/**
+ * This function is not supported on LOONGARCH.
+ */
+int
+rte_power_monitor(const struct rte_power_monitor_cond *pmc,
+ const uint64_t tsc_timestamp)
+{
+ RTE_SET_USED(pmc);
+ RTE_SET_USED(tsc_timestamp);
+
+ return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on LOONGARCH.
+ */
+int
+rte_power_pause(const uint64_t tsc_timestamp)
+{
+ RTE_SET_USED(tsc_timestamp);
+
+ return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on LOONGARCH.
+ */
+int
+rte_power_monitor_wakeup(const unsigned int lcore_id)
+{
+ RTE_SET_USED(lcore_id);
+
+ return -ENOTSUP;
+}
+
+int
+rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[],
+ const uint32_t num, const uint64_t tsc_timestamp)
+{
+ RTE_SET_USED(pmc);
+ RTE_SET_USED(num);
+ RTE_SET_USED(tsc_timestamp);
+
+ return -ENOTSUP;
+}
@@ -56,6 +56,8 @@ elif host_machine.cpu_family().startswith('ppc')
arch_subdir = 'ppc'
elif host_machine.cpu_family().startswith('riscv')
arch_subdir = 'riscv'
+elif host_machine.cpu_family().startswith('loongarch')
+ arch_subdir = 'loongarch'
endif
# configure the build, and make sure configs here and in config folder are