From patchwork Sat Aug 20 02:31:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115294 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 972A3A034C; Fri, 19 Aug 2022 20:40:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 35E4742C0E; Fri, 19 Aug 2022 20:36:47 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id EE7FE42B9F; Fri, 19 Aug 2022 20:36:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660934189; x=1692470189; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QO9OG+5UPRIDxzcpDhZsNZhTx2eA4edsZXPCt+G9bPY=; b=QXcdsD1O2c0pLR6d/N0wmYbTJ4lKUKNpLyZnlygatZJzgHnzraWBtADQ PETGhusdQJqMEbtUaGr47a334YB/QX8LMEEDYx7TdKdZHO63yxNUhIbIE 2WtSjL/1pZap8bcSO+4XvHVArhoOEObPKgXC7sthafC5pHbmhOwsfQMmD gKysQdv9WsMh7SHROOuEDmNDTlcYdX8N35hprcjlHkw3Z5lisSa/KqGBy UtVcmeBfEJ7HMV9rm4d8kysteCRcK/M+PE6qOiRfUhS5dJPyi2PsVQXo6 hROqsc26MkrNO0J7aoQTVTa/D+tufL4/8rCSv5znOK4ZPzvDe5aHOS43W g==; X-IronPort-AV: E=McAfee;i="6500,9779,10444"; a="319107344" X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="319107344" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 11:36:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="608296370" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga002.jf.intel.com with ESMTP; 19 Aug 2022 11:36:27 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v2 36/37] baseband/acc100: make HARQ layout memory 4GB Date: Fri, 19 Aug 2022 19:31:56 -0700 Message-Id: <20220820023157.189047-37-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220820023157.189047-1-hernan.vargas@intel.com> References: <20220820023157.189047-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org HARQ layout memory should be 4GB instead of 2GB. Fixes: 4cf90079797 ("baseband/acc100: add HW register definitions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc100/acc100_pmd.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h index 27801767b7..f9ccb1ea8e 100644 --- a/drivers/baseband/acc100/acc100_pmd.h +++ b/drivers/baseband/acc100/acc100_pmd.h @@ -61,8 +61,10 @@ #define ACC100_SIZE_64MBYTE (64*1024*1024) /* Number of elements in an Info Ring */ #define ACC100_INFO_RING_NUM_ENTRIES 1024 -/* Number of elements in HARQ layout memory */ -#define ACC100_HARQ_LAYOUT (64*1024*1024) +/* Number of elements in HARQ layout memory + * 128M x 32kB = 4GB addressable memory + */ +#define ACC100_HARQ_LAYOUT (128*1024*1024) /* Assume offset for HARQ in memory */ #define ACC100_HARQ_OFFSET (32*1024) #define ACC100_HARQ_OFFSET_SHIFT 15