From patchwork Sat Aug 20 02:31:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115268 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5474FA034C; Fri, 19 Aug 2022 20:37:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D98CE42B83; Fri, 19 Aug 2022 20:36:23 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 80AAF40E2D for ; Fri, 19 Aug 2022 20:36:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660934176; x=1692470176; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=njEG3/y+sSu+BkAZUfADqZWjQL4sA2V/y/scOYy6RDA=; b=B0UBpQq2yxqT3F+7XTEkRmPPfULBvpwcn8MrAjbFW4H2McmgBJ5f1KMX 3wNzP7Lm85EF7uWXAG9TDYy8oTv1hJkzvwhJStdA9Xva1x0JFNd2l9NJc 3Ho6JeHG0//EMahxyDjCSC6LX0pVjFoVq3o96F22RYDfUJnJN8/YEqtBw 0bFBS3WCwJHHBRmrXv4gQke77tHAXY3gLmSO2fmPn15YC91ck46aLYfZx hReZ7aQlmyITM5eUAmMtQQoj6sBc0v4ww3P6kkGPkHNAueAYuR4BBPzXX ERJTjHOSkuZlIjwYk8Gim+4d7ov6L5AKDkXZXHeGLeZ0waRdJgtV44iMG Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10444"; a="319107237" X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="319107237" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 11:36:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="608296270" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga002.jf.intel.com with ESMTP; 19 Aug 2022 11:36:15 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v2 10/37] baseband/acc100: avoid mux for small inbound frames Date: Fri, 19 Aug 2022 19:31:30 -0700 Message-Id: <20220820023157.189047-11-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220820023157.189047-1-hernan.vargas@intel.com> References: <20220820023157.189047-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update check_mux to avoid multiplexing small inbound frames. Preventing to multiplex code blocks when K < 512B per specs. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/acc100_pmd.h | 1 + drivers/baseband/acc100/rte_acc100_pmd.c | 16 +++++++++++----- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h index 0c9810ca56..19a1f434bc 100644 --- a/drivers/baseband/acc100/acc100_pmd.h +++ b/drivers/baseband/acc100/acc100_pmd.h @@ -135,6 +135,7 @@ #define ACC100_DEC_OFFSET (80) #define ACC100_EXT_MEM /* Default option with memory external to CPU */ #define ACC100_HARQ_OFFSET_THRESHOLD 1024 +#define ACC100_LIMIT_DL_MUX_BITS 534 /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ #define ACC100_N_ZC_1 66 /* N = 66 Zc for BG 1 */ diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 5d09908fd0..71409e11a1 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -3548,20 +3548,25 @@ acc100_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data, } /* Check we can mux encode operations with common FCW */ -static inline bool +static inline int16_t check_mux(struct rte_bbdev_enc_op **ops, uint16_t num) { uint16_t i; if (num <= 1) - return false; + return 1; for (i = 1; i < num; ++i) { /* Only mux compatible code blocks */ if (memcmp((uint8_t *)(&ops[i]->ldpc_enc) + ACC100_ENC_OFFSET, (uint8_t *)(&ops[0]->ldpc_enc) + ACC100_ENC_OFFSET, ACC100_CMP_ENC_SIZE) != 0) - return false; + return i; } - return true; + /* Avoid multiplexing small inbound size frames */ + int Kp = (ops[0]->ldpc_enc.basegraph == 1 ? 22 : 10) * + ops[0]->ldpc_enc.z_c - ops[0]->ldpc_enc.n_filler; + if (Kp <= ACC100_LIMIT_DL_MUX_BITS) + return 1; + return num; } /** Enqueue encode operations for ACC100 device in CB mode. */ @@ -3583,7 +3588,8 @@ acc100_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data, } avail--; enq = RTE_MIN(left, ACC100_MUX_5GDL_DESC); - if (check_mux(&ops[i], enq)) { + enq = check_mux(&ops[i], enq); + if (enq > 1) { ret = enqueue_ldpc_enc_n_op_cb(q, &ops[i], desc_idx, enq); if (ret < 0) {