diff mbox series

net/mlx5: fix the inline length exceeding descriptor limit

Message ID 20220817141357.7386-1-viacheslavo@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: fix the inline length exceeding descriptor limit |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/github-robot: build success github build: passed
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS

Commit Message

Slava Ovsiienko Aug. 17, 2022, 2:13 p.m. UTC 
  The hardware descriptor (WQE) length field is 6 bits wide
and we have the native limitation for the overall descriptor
length. To improve the PCIe bandwidth the packet data can be
inline into descriptor. If PMD was configured to inline large
amount of data it happened there was no enough space remaining
in the descriptor to specify all the packet data segments and
PMD rejected problematic packets.

The patch tries to adjust the inline data length conservatively
and allows to avoid error occurring.

Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template")
Fixes: e2259f93ef45 ("net/mlx5: fix Tx when inlining is impossible")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Reviewed-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
---
 drivers/net/mlx5/mlx5_tx.h | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

Comments

Raslan Darawsheh Aug. 18, 2022, 11:07 a.m. UTC | #1 
Hi,

> -----Original Message-----
> From: Slava Ovsiienko <viacheslavo@nvidia.com>
> Sent: Wednesday, August 17, 2022 5:14 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Raslan Darawsheh
> <rasland@nvidia.com>; Dmitry Kozlyuk <dkozlyuk@nvidia.com>;
> stable@dpdk.org
> Subject: [PATCH] net/mlx5: fix the inline length exceeding descriptor limit
> 
> The hardware descriptor (WQE) length field is 6 bits wide
> and we have the native limitation for the overall descriptor
> length. To improve the PCIe bandwidth the packet data can be
> inline into descriptor. If PMD was configured to inline large
> amount of data it happened there was no enough space remaining
> in the descriptor to specify all the packet data segments and
> PMD rejected problematic packets.
> 
> The patch tries to adjust the inline data length conservatively
> and allows to avoid error occurring.
> 
> Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template")
> Fixes: e2259f93ef45 ("net/mlx5: fix Tx when inlining is impossible")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> Reviewed-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h
index 8e113e3778..59ebe95032 100644
--- a/drivers/net/mlx5/mlx5_tx.h
+++ b/drivers/net/mlx5/mlx5_tx.h
@@ -2078,8 +2078,24 @@  mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
 	if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
 		return MLX5_TXCMP_CODE_EXIT;
 	/* Check for maximal WQE size. */
-	if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ds))
-		return MLX5_TXCMP_CODE_ERROR;
+	if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ds)) {
+		/*  Check if we can adjust the inline length. */
+		if (unlikely(txq->inlen_mode)) {
+			ds = NB_SEGS(loc->mbuf) + 2 +
+				(txq->inlen_mode -
+				MLX5_ESEG_MIN_INLINE_SIZE +
+				MLX5_WSEG_SIZE +
+				MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
+			if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ds))
+				return MLX5_TXCMP_CODE_ERROR;
+		}
+		/* We have lucky opportunity to adjust. */
+		inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX -
+				       MLX5_WSEG_SIZE * 2 -
+				       MLX5_WSEG_SIZE * NB_SEGS(loc->mbuf) -
+				       MLX5_WSEG_SIZE +
+				       MLX5_ESEG_MIN_INLINE_SIZE);
+	}
 #ifdef MLX5_PMD_SOFT_COUNTERS
 	/* Update sent data bytes/packets counters. */
 	txq->stats.obytes += dlen + vlan;