From patchwork Tue Aug 16 05:52:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115115 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E29A9A00C3; Mon, 15 Aug 2022 23:58:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F2F2342B6D; Mon, 15 Aug 2022 23:57:40 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id D2F22427F0 for ; Mon, 15 Aug 2022 23:57:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600655; x=1692136655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pYFOrOtbYC/cHtu+I4NTp6AQY5Jb8bYV9qnyul+d9Z0=; b=InWqWk5RXNCzxlGfz3EMqAaVoj9ZfbSozQ2odxqP2gyf/lAQUFv/u9dv v1eDhNm2OC0rTzIH+mCZejecjxKniIwEaqak9nrGha54HOQ74pX21Rjn3 hmqxUlm1zety17Gn/yu2kXUb2oHh22XHHCeQoLUfqvze6qdLEnFPmNPro 0I+Tq59oeSEOa23axDKWIUekW+EOy1J1ImMGALObm20yEae1fvj8tbnX/ sHOfC/DgeTy21tvW32mWdYkXaxQ8Zui1+Rg9dOKdZv99GRe3w6EdaC0yk aq7zGIT1GXRCNUcphLqWKqHesTizYjyTbKvv4iK/62ipHZukyBcnDMnsy Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862711" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862711" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826036" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:33 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 07/33] baseband/acc100: avoid mux for small inbound frames Date: Mon, 15 Aug 2022 22:52:32 -0700 Message-Id: <20220816055258.107564-8-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update check_mux to avoid multiplexing small inbound frames. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 97e4078a24..fbd6605802 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -3551,20 +3551,25 @@ acc100_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data, } /* Check we can mux encode operations with common FCW */ -static inline bool +static inline int16_t check_mux(struct rte_bbdev_enc_op **ops, uint16_t num) { uint16_t i; if (num <= 1) - return false; + return 1; for (i = 1; i < num; ++i) { /* Only mux compatible code blocks */ if (memcmp((uint8_t *)(&ops[i]->ldpc_enc) + ACC100_ENC_OFFSET, (uint8_t *)(&ops[0]->ldpc_enc) + ACC100_ENC_OFFSET, ACC100_CMP_ENC_SIZE) != 0) - return false; + return i; } - return true; + /* Avoid multiplexing small inbound size frames */ + int Kp = (ops[0]->ldpc_enc.basegraph == 1 ? 22 : 10) * + ops[0]->ldpc_enc.z_c - ops[0]->ldpc_enc.n_filler; + if (Kp <= ACC100_LIMIT_DL_MUX_BITS) + return 1; + return num; } /** Enqueue encode operations for ACC100 device in CB mode. */ @@ -3586,7 +3591,8 @@ acc100_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data, } avail--; enq = RTE_MIN(left, ACC100_MUX_5GDL_DESC); - if (check_mux(&ops[i], enq)) { + enq = check_mux(&ops[i], enq); + if (enq > 1) { ret = enqueue_ldpc_enc_n_op_cb(q, &ops[i], desc_idx, enq); if (ret < 0) {