From patchwork Tue Aug 16 05:52:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115131 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A78B2A00C3; Tue, 16 Aug 2022 00:00:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 37B5342BEB; Mon, 15 Aug 2022 23:57:55 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 9DF5D4282B for ; Mon, 15 Aug 2022 23:57:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600659; x=1692136659; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AqbK5MszwyJ3YaCN/RhGXecoBuo/AKl7B04/C3yHmT0=; b=VWTkxZ+RBjoTLLwzbm6xpewjS51GnbvltnuQT0BpTieOcfBZZicFlaUx 0zaqJ5yvLq6pU2+0lLY1ObBnqEOoAgsvyXa9YCDJnqWrYVg1ce5O/Pi2H saOLag6Wiiv1kIW5FUPIy1ZXog/sXtsg9XKKSJ+fPSva74GwilnSwHMBZ qAzG6dVmFc6Wcu5bF7RfzwCZmIBOhQiei/BkRCtWfMxiPs7VP+F1DqNAI 8CohntQo9oMgLbbp/M/tphmsXJLECgtj1iFXVkcFcs7wiNcjz9TS8RqRk +XdCMkcbXlMX8NeaWvgw8MpU1eqJ/IE0CEJn5JdHQKe0Tp7SNOxanjM0I g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862735" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862735" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826098" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:38 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 23/33] baseband/acc100: update log messages Date: Mon, 15 Aug 2022 22:52:48 -0700 Message-Id: <20220816055258.107564-24-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add extra values for some log messages. No functional impact. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 93d6db740d..8240df76cc 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1173,6 +1173,7 @@ acc100_dev_info_get(struct rte_bbdev *dev, /* Read and save the populated config from ACC100 registers */ fetch_acc100_config(dev); + /* Check the status of device */ dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; /* Expose number of queues */ @@ -3255,7 +3256,7 @@ enqueue_ldpc_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, { #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE if (validate_ldpc_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC encoder validation failed"); + rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif @@ -4178,8 +4179,9 @@ acc100_enqueue_status(struct rte_bbdev_queue_data *q_data, { q_data->enqueue_status = status; q_data->queue_stats.enqueue_status_count[status]++; - rte_bbdev_log(WARNING, "Enqueue Status: %d %#"PRIx64"", - status, + + rte_bbdev_log(WARNING, "Enqueue Status: %s %#"PRIx64"", + rte_bbdev_enqueue_status_str(status), q_data->queue_stats.enqueue_status_count[status]); } @@ -4879,6 +4881,7 @@ dequeue_ldpc_dec_one_op_cb(struct rte_bbdev_queue_data *q_data, return -1; rsp.val = atom_desc.rsp.val; + rte_bbdev_log_debug("Resp. desc %p: %x\n", desc, rsp.val); /* Dequeue */ op = desc->req.op_addr; @@ -4961,8 +4964,9 @@ dequeue_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op **ref_op, atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); rsp.val = atom_desc.rsp.val; - rte_bbdev_log_debug("Resp. desc %p: %x", desc, - rsp.val); + rte_bbdev_log_debug("Resp. desc %p: %x r %d c %d\n", + desc, rsp.val, + cb_idx, cbs_in_tb); op->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);