From patchwork Tue Aug 9 18:48:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114784 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 57A2AA04FD; Tue, 9 Aug 2022 20:52:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 42F3242BCB; Tue, 9 Aug 2022 20:52:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B98D04113F for ; Tue, 9 Aug 2022 20:51:58 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279D8BCo017014; Tue, 9 Aug 2022 11:49:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=uDE0sCdPRek9xq25exzNTEi4Ptlz4rmPh8eC8skAES8=; b=I48jhw/FMSDCH1U6lxq+hIvaKDGLI9ZfFENllKTnwCWQim43EVE/Zxvk3h/sbT5eYV5p jFoxjGbvB6XnUd6XqF+w0IKAYWTfvnLTQAVbGRDtrRjX5EzWGB+L3Phzr+LqeeenjpSr CE8Qwa8L2HyKl66ibzwL8/l4Z4JeqL8Ltfsmgf4xFdGuOk44OllWEX3ZC45ejSZizV+Q ciDdNWUBJ+w5OPPhP3rj/OhMVAhQeb6tcRGmO761G1jEQf2483/7VcbRw5RKL66MAWbm Juml0yAC1T4kz8psS7AsQKU1+7eIX4T3SCpKLnwY0z/2rR1ylsQyiyB9yjkkxwpM7LHc Ow== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hudy6ujpy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 09 Aug 2022 11:49:53 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Aug 2022 11:49:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 9 Aug 2022 11:49:51 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 160FE3F7085; Tue, 9 Aug 2022 11:49:48 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , , Srujana Challa Subject: [PATCH 03/23] common/cnxk: update inbound inline IPsec config mailbox Date: Wed, 10 Aug 2022 00:18:47 +0530 Message-ID: <20220809184908.24030-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ZphHo3-QxAHnv12jzs-nV-h45Y3Wa0nj X-Proofpoint-ORIG-GUID: ZphHo3-QxAHnv12jzs-nV-h45Y3Wa0nj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Srujana Challa Updates CPT inbound inline IPsec configuration mailbox to provide opcode and CPT credit from VF. This patch also adds mailbox for reading inbound IPsec configuration. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_cpt.c | 15 +++++++++++++++ drivers/common/cnxk/roc_cpt.h | 2 ++ drivers/common/cnxk/roc_mbox.h | 12 +++++++++--- drivers/common/cnxk/version.map | 1 + 4 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index f1be6a3..d607bde 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -261,6 +261,21 @@ roc_cpt_inline_ipsec_cfg(struct dev *cpt_dev, uint8_t lf_id, } int +roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt, + struct nix_inline_ipsec_cfg *inb_cfg) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct dev *dev = &cpt->dev; + struct msg_req *req; + + req = mbox_alloc_msg_nix_read_inline_ipsec_cfg(dev->mbox); + if (req == NULL) + return -EIO; + + return mbox_process_msg(dev->mbox, (void *)&inb_cfg); +} + +int roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1, uint16_t param2) { diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index a3a65f1..4e3a078 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -158,6 +158,8 @@ int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, int __roc_api roc_cpt_lf_ctx_reload(struct roc_cpt_lf *lf, void *cptr); int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot, struct roc_nix *nix); +int __roc_api roc_cpt_inline_ipsec_inb_cfg_read( + struct roc_cpt *roc_cpt, struct nix_inline_ipsec_cfg *inb_cfg); int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1, uint16_t param2); int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt); diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 965c704..912de11 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -263,7 +263,9 @@ struct mbox_msghdr { nix_bp_cfg_rsp) \ M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \ msg_rsp) \ - M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) + M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) \ + M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ + msg_req, nix_inline_ipsec_cfg) /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -1161,7 +1163,9 @@ struct nix_inline_ipsec_cfg { uint32_t __io cpt_credit; struct { uint8_t __io egrp; - uint8_t __io opcode; + uint16_t __io opcode; + uint16_t __io param1; + uint16_t __io param2; } gen_cfg; struct { uint16_t __io cpt_pf_func; @@ -1465,7 +1469,9 @@ struct cpt_rx_inline_lf_cfg_msg { uint16_t __io sso_pf_func; uint16_t __io param1; uint16_t __io param2; - uint16_t __io reserved; + uint16_t __io opcode; + uint32_t __io credit; + uint32_t __io reserved; }; enum cpt_eng_type { diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 019f531..a2d99e1 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -65,6 +65,7 @@ INTERNAL { roc_cpt_dev_init; roc_cpt_eng_grp_add; roc_cpt_inline_ipsec_cfg; + roc_cpt_inline_ipsec_inb_cfg_read; roc_cpt_inline_ipsec_inb_cfg; roc_cpt_iq_disable; roc_cpt_iq_enable;