From patchwork Fri Jul 29 19:30:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xiaoyun" X-Patchwork-Id: 114458 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7C69A00C4; Fri, 29 Jul 2022 21:32:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 16D2742C80; Fri, 29 Jul 2022 21:31:19 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 387C642C6D for ; Fri, 29 Jul 2022 21:31:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659123077; x=1690659077; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ygJySkLLIsoclOGexHoGWrJk2VPWwtHVKnwuj4qsurw=; b=KEHG+8QSGf7z6uTo01lK+0s/LED2ZBcDywCOgvN8r9Yw3DFrMjnhOAyq HGiMFl9rSuE0pTvSvEfi8rAAFA/dgSqywZKifyVRljDnB22/65SDS7vo1 su4JyJU2kTDw2cWLpHZOU55rRJb7VYAG8v4wh9tK7WqDv3iDmSX9eLCHG 2NwwusJSErl6778w6MigX6Z+UHQD31dgBj74n8WnRR1g6ghU+I9jDfiMP bKxnrj8oNMcA9D3AKpVotlVfWDzjuW0p6JcecTcrBdHwbymUKHutm0AHM O1B7aKmAwRLsknmPP52rFUNCEUvHrM2Uj2nYgqOIGUKS5gheZnGy+NNI6 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10423"; a="268602968" X-IronPort-AV: E=Sophos;i="5.93,201,1654585200"; d="scan'208";a="268602968" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2022 12:31:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,201,1654585200"; d="scan'208";a="577059579" Received: from silpixa00399779.ir.intel.com (HELO silpixa00399779.ger.corp.intel.com) ([10.237.223.111]) by orsmga006.jf.intel.com with ESMTP; 29 Jul 2022 12:31:15 -0700 From: Xiaoyun Li To: junfeng.guo@intel.com, qi.z.zhang@intel.com, awogbemila@google.com, bruce.richardson@intel.com Cc: dev@dpdk.org, Xiaoyun Li Subject: [PATCH 08/10] net/gve: add support to get dev info and configure dev Date: Fri, 29 Jul 2022 19:30:40 +0000 Message-Id: <20220729193042.2764633-9-xiaoyun.li@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220729193042.2764633-1-xiaoyun.li@intel.com> References: <20220729193042.2764633-1-xiaoyun.li@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add dev_ops dev_infos_get. Complete dev_configure with RX offloads configuration. Signed-off-by: Xiaoyun Li --- drivers/net/gve/gve.h | 3 ++ drivers/net/gve/gve_ethdev.c | 61 ++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/drivers/net/gve/gve.h b/drivers/net/gve/gve.h index 7f4d0e37f3..004e0a75ca 100644 --- a/drivers/net/gve/gve.h +++ b/drivers/net/gve/gve.h @@ -27,6 +27,9 @@ #define GVE_DEFAULT_TX_FREE_THRESH 256 #define GVE_TX_MAX_FREE_SZ 512 +#define GVE_MIN_BUF_SIZE 1024 +#define GVE_MAX_RX_PKTLEN 65535 + /* PTYPEs are always 10 bits. */ #define GVE_NUM_PTYPES 1024 diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c index 5ebe2c30ea..6bc7bf4519 100644 --- a/drivers/net/gve/gve_ethdev.c +++ b/drivers/net/gve/gve_ethdev.c @@ -96,6 +96,14 @@ gve_free_qpls(struct gve_priv *priv) static int gve_dev_configure(__rte_unused struct rte_eth_dev *dev) { + struct gve_priv *priv = dev->data->dev_private; + + if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) + dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; + + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) + priv->enable_lsc = 1; + return 0; } @@ -266,6 +274,58 @@ gve_dev_close(struct rte_eth_dev *dev) return err; } +static int +gve_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) +{ + struct gve_priv *priv = dev->data->dev_private; + + dev_info->device = dev->device; + dev_info->max_mac_addrs = 1; + dev_info->max_rx_queues = priv->max_nb_rxq; + dev_info->max_tx_queues = priv->max_nb_txq; + dev_info->min_rx_bufsize = GVE_MIN_BUF_SIZE; + dev_info->max_rx_pktlen = GVE_MAX_RX_PKTLEN; + + dev_info->rx_offload_capa = 0; + dev_info->tx_offload_capa = + RTE_ETH_TX_OFFLOAD_MULTI_SEGS | + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_TX_OFFLOAD_UDP_CKSUM | + RTE_ETH_TX_OFFLOAD_TCP_CKSUM | + RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | + RTE_ETH_TX_OFFLOAD_TCP_TSO; + + if (priv->queue_format == GVE_DQO_RDA_FORMAT) + dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TCP_LRO; + + dev_info->default_rxconf = (struct rte_eth_rxconf) { + .rx_free_thresh = GVE_DEFAULT_RX_FREE_THRESH, + .rx_drop_en = 0, + .offloads = 0, + }; + + dev_info->default_txconf = (struct rte_eth_txconf) { + .tx_free_thresh = GVE_DEFAULT_TX_FREE_THRESH, + .offloads = 0, + }; + + dev_info->default_rxportconf.ring_size = priv->rx_desc_cnt; + dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = priv->rx_desc_cnt, + .nb_min = priv->rx_desc_cnt, + .nb_align = 1, + }; + + dev_info->default_txportconf.ring_size = priv->tx_desc_cnt; + dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = priv->tx_desc_cnt, + .nb_min = priv->tx_desc_cnt, + .nb_align = 1, + }; + + return 0; +} + static int gve_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) { @@ -299,6 +359,7 @@ static const struct eth_dev_ops gve_eth_dev_ops = { .dev_start = gve_dev_start, .dev_stop = gve_dev_stop, .dev_close = gve_dev_close, + .dev_infos_get = gve_dev_info_get, .rx_queue_setup = gve_rx_queue_setup, .tx_queue_setup = gve_tx_queue_setup, .link_update = gve_link_update,