@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2020 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/fib.spec /tmp/fib.c
+pipeline libbuild /tmp/fib.c /tmp/fib.so
+
;
; Customize the LINK parameters to match your setup.
;
@@ -26,7 +32,7 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/fib.spec
+pipeline PIPELINE0 build /tmp/fib.so
;
; Initial set of table entries.
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2022 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/hash_func.spec /tmp/hash_func.c
+pipeline libbuild /tmp/hash_func.c /tmp/hash_func.so
+
;
; Customize the LINK parameters to match your setup.
;
@@ -26,7 +32,7 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/hash_func.spec
+pipeline PIPELINE0 build /tmp/hash_func.so
;
; Pipelines-to-threads mapping.
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2020 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/l2fwd.spec /tmp/l2fwd.c
+pipeline libbuild /tmp/l2fwd.c /tmp/l2fwd.so
+
mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
@@ -20,6 +26,6 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/l2fwd.spec
+pipeline PIPELINE0 build /tmp/l2fwd.so
thread 1 pipeline PIPELINE0 enable
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2020 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/l2fwd_macswp.spec /tmp/l2fwd_macswp.c
+pipeline libbuild /tmp/l2fwd_macswp.c /tmp/l2fwd_macswp.so
+
mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
@@ -20,6 +26,6 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/l2fwd_macswp.spec
+pipeline PIPELINE0 build /tmp/l2fwd_macswp.so
thread 1 pipeline PIPELINE0 enable
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2020 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/l2fwd_macswp.spec /tmp/l2fwd_macswp.c
+pipeline libbuild /tmp/l2fwd_macswp.c /tmp/l2fwd_macswp.so
+
mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
pipeline PIPELINE0 create 0
@@ -15,6 +21,6 @@ pipeline PIPELINE0 port out 1 sink none
pipeline PIPELINE0 port out 2 sink none
pipeline PIPELINE0 port out 3 sink none
-pipeline PIPELINE0 build ./examples/pipeline/examples/l2fwd_macswp.spec
+pipeline PIPELINE0 build /tmp/l2fwd_macswp.so
thread 1 pipeline PIPELINE0 enable
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2020 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/l2fwd.spec /tmp/l2fwd.c
+pipeline libbuild /tmp/l2fwd.c /tmp/l2fwd.so
+
mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
pipeline PIPELINE0 create 0
@@ -15,6 +21,6 @@ pipeline PIPELINE0 port out 1 sink none
pipeline PIPELINE0 port out 2 sink none
pipeline PIPELINE0 port out 3 sink none
-pipeline PIPELINE0 build ./examples/pipeline/examples/l2fwd.spec
+pipeline PIPELINE0 build /tmp/l2fwd.so
thread 1 pipeline PIPELINE0 enable
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2020 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/learner.spec /tmp/learner.c
+pipeline libbuild /tmp/learner.c /tmp/learner.so
+
;
; Customize the LINK parameters to match your setup.
;
@@ -26,7 +32,7 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/learner.spec
+pipeline PIPELINE0 build /tmp/learner.so
;
; Pipelines-to-threads mapping.
@@ -4,6 +4,12 @@
; Example command line:
; ./build/examples/dpdk-pipeline -l0-1 -- -s ./examples/pipeline/examples/meter.cli
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/meter.spec /tmp/meter.c
+pipeline libbuild /tmp/meter.c /tmp/meter.so
+
mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
@@ -23,7 +29,7 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/meter.spec
+pipeline PIPELINE0 build /tmp/meter.so
pipeline PIPELINE0 meter profile platinum add cir 46000000 pir 138000000 cbs 1000000 pbs 1000000
pipeline PIPELINE0 meter meters from 0 to 15 set profile platinum
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2022 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/mirroring.spec /tmp/mirroring.c
+pipeline libbuild /tmp/mirroring.c /tmp/mirroring.so
+
;
; Customize the LINK parameters to match your setup.
;
@@ -27,7 +33,7 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/mirroring.spec
+pipeline PIPELINE0 build /tmp/mirroring.so
;
; Packet mirroring sessions.
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2022 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/recirculation.spec /tmp/recirculation.c
+pipeline libbuild /tmp/recirculation.c /tmp/recirculation.so
+
;
; Customize the LINK parameters to match your setup.
;
@@ -26,7 +32,7 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/recirculation.spec
+pipeline PIPELINE0 build /tmp/recirculation.so
;
; Pipelines-to-threads mapping.
@@ -4,6 +4,12 @@
; Example command line:
; ./build/examples/dpdk-pipeline -l0-1 -- -s ./examples/pipeline/examples/registers.cli
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/registers.spec /tmp/registers.c
+pipeline libbuild /tmp/registers.c /tmp/registers.so
+
mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
@@ -23,6 +29,6 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/registers.spec
+pipeline PIPELINE0 build /tmp/registers.so
thread 1 pipeline PIPELINE0 enable
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2020 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/selector.spec /tmp/selector.c
+pipeline libbuild /tmp/selector.c /tmp/selector.so
+
mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
@@ -20,7 +26,7 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/selector.spec
+pipeline PIPELINE0 build /tmp/selector.so
pipeline PIPELINE0 selector s group add
pipeline PIPELINE0 selector s group member add ./examples/pipeline/examples/selector.txt
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2020 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/varbit.spec /tmp/varbit.c
+pipeline libbuild /tmp/varbit.c /tmp/varbit.so
+
;
; Customize the LINK parameters to match your setup.
;
@@ -26,7 +32,7 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/varbit.spec
+pipeline PIPELINE0 build /tmp/varbit.so
;
; Pipelines-to-threads mapping.
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2020 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/vxlan.spec /tmp/vxlan.c
+pipeline libbuild /tmp/vxlan.c /tmp/vxlan.so
+
mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
@@ -20,7 +26,7 @@ pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec
+pipeline PIPELINE0 build /tmp/vxlan.so
pipeline PIPELINE0 table vxlan_table add ./examples/pipeline/examples/vxlan_table.txt
pipeline PIPELINE0 commit
@@ -1,6 +1,12 @@
; SPDX-License-Identifier: BSD-3-Clause
; Copyright(c) 2020 Intel Corporation
+;
+; Pipeline code generation & shared object library build
+;
+pipeline codegen ./examples/pipeline/examples/vxlan.spec /tmp/vxlan.c
+pipeline libbuild /tmp/vxlan.c /tmp/vxlan.so
+
mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
pipeline PIPELINE0 create 0
@@ -15,7 +21,7 @@ pipeline PIPELINE0 port out 1 sink none
pipeline PIPELINE0 port out 2 sink none
pipeline PIPELINE0 port out 3 sink none
-pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec
+pipeline PIPELINE0 build /tmp/vxlan.so
pipeline PIPELINE0 table vxlan_table add ./examples/pipeline/examples/vxlan_table.txt
pipeline PIPELINE0 commit