From patchwork Thu Jun 30 15:41:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 113578 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1E6D6A00C4; Thu, 30 Jun 2022 17:41:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0B24540A7D; Thu, 30 Jun 2022 17:41:35 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D52614069D for ; Thu, 30 Jun 2022 17:41:33 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25UB19CO032130; Thu, 30 Jun 2022 08:41:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=1NO6GZD6rNEn+jXBnTaP/VFeeAyuiWLkhR9WTS6MKcU=; b=AWIuLO4fDDHRabr1uGipcH+rP/hDVBZFGwixU9ujMEG53+9ABQmPoHWIA/KouqJCC+gi gK8XfDu59gVhaw8uXDJ++3Y86JaSwl8savJMMlc7WzYWG0UEpBaOM0X0QrVaOtaVpwsd 4gWZOcbeYW9sNM3boG9V5/Sf7IiS+F0FSHjCT53fm/JRTFOneWFtNTMMTmivrhfifEXH adcTe/Q3MdBjlDHLEMhFAmP0r7c6Z1E+Tk1qn6V3w57KACbuyjSBdGJ1zYl3QL2EF5pK yK6kolhQ27H8WTUWGbf2MGfRdPw9O8hKIuhGmuNZ5EnRhGmvhqKXta0wFnWj5HG0Oj7p +g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3h1akbh50f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 30 Jun 2022 08:41:32 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jun 2022 08:41:31 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jun 2022 08:41:31 -0700 Received: from localhost.localdomain (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id A88C23F7077; Thu, 30 Jun 2022 08:41:26 -0700 (PDT) From: Ashwin Sekhar T K To: , Fan Zhang , Pablo de Lara CC: , , , , , , , , , , Subject: [PATCH v2] crypto/ipsec_mb: enable support for arm64 Date: Thu, 30 Jun 2022 21:11:23 +0530 Message-ID: <20220630154123.2565439-1-asekhar@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220610162836.1828084-1-asekhar@marvell.com> References: <20220610162836.1828084-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: uWaX7BsTbDVJWcwxW5rVk8mkCMMBySWO X-Proofpoint-ORIG-GUID: uWaX7BsTbDVJWcwxW5rVk8mkCMMBySWO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-06-30_10,2022-06-28_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable support for arm64 architecture in ipsec_mb. x86 specific code is conditionally compiled only for x86 architecture builds. Other architectures will be unsupported. Signed-off-by: Ashwin Sekhar T K Acked-by: Fan Zhang --- drivers/crypto/ipsec_mb/ipsec_mb_private.c | 7 +++++++ drivers/crypto/ipsec_mb/ipsec_mb_private.h | 3 ++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/ipsec_mb/ipsec_mb_private.c b/drivers/crypto/ipsec_mb/ipsec_mb_private.c index aab42c360c..b555a28a0b 100644 --- a/drivers/crypto/ipsec_mb/ipsec_mb_private.c +++ b/drivers/crypto/ipsec_mb/ipsec_mb_private.c @@ -53,6 +53,9 @@ ipsec_mb_create(struct rte_vdev_device *vdev, const char *name, *args; int retval; +#if defined(RTE_ARCH_ARM64) + vector_mode = IPSEC_MB_ARM64; +#elif defined(RTE_ARCH_X86_64) if (vector_mode == IPSEC_MB_NOT_SUPPORTED) { /* Check CPU for supported vector instruction set */ if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) @@ -64,6 +67,10 @@ ipsec_mb_create(struct rte_vdev_device *vdev, else vector_mode = IPSEC_MB_SSE; } +#else + /* Unsupported architecture */ + return -ENOTSUP; +#endif init_params.private_data_size = sizeof(struct ipsec_mb_dev_private) + pmd_data->internals_priv_size; diff --git a/drivers/crypto/ipsec_mb/ipsec_mb_private.h b/drivers/crypto/ipsec_mb/ipsec_mb_private.h index e2c240dfc0..d0a1bcc360 100644 --- a/drivers/crypto/ipsec_mb/ipsec_mb_private.h +++ b/drivers/crypto/ipsec_mb/ipsec_mb_private.h @@ -26,7 +26,8 @@ enum ipsec_mb_vector_mode { IPSEC_MB_SSE, IPSEC_MB_AVX, IPSEC_MB_AVX2, - IPSEC_MB_AVX512 + IPSEC_MB_AVX512, + IPSEC_MB_ARM64, }; extern enum ipsec_mb_vector_mode vector_mode;