From patchwork Thu Jun 16 07:07:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 112838 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 32533A00C3; Thu, 16 Jun 2022 09:09:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2731C42BD1; Thu, 16 Jun 2022 09:09:59 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id CCB0442BCA for ; Thu, 16 Jun 2022 09:09:57 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25FN9p0V014305 for ; Thu, 16 Jun 2022 00:09:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=psjGFqjfwk3xpLtzmqCfyANN058bufBwdQgFS5iuVyg=; b=XS4ZgzU7AaczO/0bsOHwhSu0anqyOe9woITy5KhL3Ao6ntNdVSqOERoUTCTEWTKQ+nw5 6OyfY9P07PRBHrUlWMcWOOJm3emGN+bfOfaWFg11JL19M5aEL7djXH776VG2QZsQbsqT HIBE7FyTVtbfGc+wxmYw20df5i/Gxb5CkeoHeLdrPqvfVXq+3QtGO2/mdnAgkh5IqnkU zlaPymXxNed0GI7C88aj5RI+RjeWAeic1QmYmQZ1uIVvnATnbYzZ2jWytusla/j2qwms j13j+luNz7h/z/4dKJldyNLenaI/uZUlFcV9x7NFybfgsnwKHa29pM6pacN02QFlQ6Wa 3A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3gqruu9khf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 16 Jun 2022 00:09:56 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 16 Jun 2022 00:09:55 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 16 Jun 2022 00:09:55 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 247363F703F; Thu, 16 Jun 2022 00:09:52 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Harman Kalra Subject: [PATCH 09/12] net/cnxk: pfc class disable resulting in invalid behaviour Date: Thu, 16 Jun 2022 12:37:40 +0530 Message-ID: <20220616070743.30658-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220616070743.30658-1-ndabilpuram@marvell.com> References: <20220616070743.30658-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ShwKdLdkyVQKDluP9wkwzexdJ3h0_wsc X-Proofpoint-GUID: ShwKdLdkyVQKDluP9wkwzexdJ3h0_wsc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-16_03,2022-06-15_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Harman Kalra Disabling a specific pfc class on a SQ is resulting in disabling PFC on the entire port. Signed-off-by: Harman Kalra Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cnxk_ethdev.c | 25 ++++++++++++------------- drivers/net/cnxk/cnxk_ethdev.h | 1 - drivers/net/cnxk/cnxk_ethdev_ops.c | 34 +++++++++++++++++++++++++++------- 3 files changed, 39 insertions(+), 21 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 941b270..4ea1617 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -439,6 +439,7 @@ cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, sq->qid = qid; sq->nb_desc = nb_desc; sq->max_sqe_sz = nix_sq_max_sqe_sz(dev); + sq->tc = ROC_NIX_PFC_CLASS_INVALID; rc = roc_nix_sq_init(&dev->nix, sq); if (rc) { @@ -1281,8 +1282,6 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) goto cq_fini; } - /* Initialize TC to SQ mapping as invalid */ - memset(dev->pfc_tc_sq_map, 0xFF, sizeof(dev->pfc_tc_sq_map)); /* * Restore queue config when reconfigure followed by * reconfigure and no queue configure invoked from application case. @@ -1794,17 +1793,17 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset) rc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf); pfc_conf.mode = RTE_ETH_FC_NONE; - for (i = 0; i < CNXK_NIX_PFC_CHAN_COUNT; i++) { - if (dev->pfc_tc_sq_map[i] != 0xFFFF) { - pfc_conf.rx_pause.tx_qid = dev->pfc_tc_sq_map[i]; - pfc_conf.rx_pause.tc = i; - pfc_conf.tx_pause.tc = i; - rc = cnxk_nix_priority_flow_ctrl_queue_config(eth_dev, - &pfc_conf); - if (rc) - plt_err("Failed to reset PFC. error code(%d)", - rc); - } + for (i = 0; i < RTE_MAX(eth_dev->data->nb_rx_queues, + eth_dev->data->nb_tx_queues); + i++) { + pfc_conf.rx_pause.tc = ROC_NIX_PFC_CLASS_INVALID; + pfc_conf.rx_pause.tx_qid = i; + pfc_conf.tx_pause.tc = ROC_NIX_PFC_CLASS_INVALID; + pfc_conf.tx_pause.rx_qid = i; + rc = cnxk_nix_priority_flow_ctrl_queue_config(eth_dev, + &pfc_conf); + if (rc) + plt_err("Failed to reset PFC. error code(%d)", rc); } /* Disable and free rte_meter entries */ diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index db2d849..a4e96f0 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -396,7 +396,6 @@ struct cnxk_eth_dev { struct cnxk_eth_qconf *rx_qconf; /* Flow control configuration */ - uint16_t pfc_tc_sq_map[CNXK_NIX_PFC_CHAN_COUNT]; struct cnxk_pfc_cfg pfc_cfg; struct cnxk_fc_cfg fc_cfg; diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index caace9d..1592971 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -1129,8 +1129,10 @@ nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev *eth_dev, uint16_t qid, struct rte_eth_dev_data *data = eth_dev->data; struct cnxk_pfc_cfg *pfc = &dev->pfc_cfg; struct roc_nix *nix = &dev->nix; + struct roc_nix_pfc_cfg pfc_cfg; struct roc_nix_fc_cfg fc_cfg; struct cnxk_eth_txq_sp *txq; + enum roc_nix_fc_mode mode; struct roc_nix_sq *sq; int rc; @@ -1140,12 +1142,6 @@ nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev *eth_dev, uint16_t qid, if (qid >= eth_dev->data->nb_tx_queues) return -ENOTSUP; - if (dev->pfc_tc_sq_map[tc] != 0xFFFF && - dev->pfc_tc_sq_map[tc] != qid) { - plt_err("Same TC can not be configured on multiple SQs"); - return -ENOTSUP; - } - /* Check if RX pause frame is enabled or not */ if (!pfc->rx_pause_en) { if ((roc_nix_tm_tree_type_get(nix) == ROC_NIX_TM_DEFAULT) && @@ -1180,7 +1176,31 @@ nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev *eth_dev, uint16_t qid, if (rc) return rc; - dev->pfc_tc_sq_map[tc] = sq->qid; + /* Maintaining a count for SQs which are configured for PFC. This is + * required to handle disabling of a particular SQ without affecting + * PFC on other SQs. + */ + if (!fc_cfg.tm_cfg.enable && sq->tc != ROC_NIX_PFC_CLASS_INVALID) { + sq->tc = ROC_NIX_PFC_CLASS_INVALID; + pfc->rx_pause_en--; + } else if (fc_cfg.tm_cfg.enable && + sq->tc == ROC_NIX_PFC_CLASS_INVALID) { + sq->tc = tc; + pfc->rx_pause_en++; + } + + if (pfc->rx_pause_en > 1) + goto exit; + + if (pfc->tx_pause_en) + mode = pfc->rx_pause_en ? ROC_NIX_FC_FULL : ROC_NIX_FC_TX; + else + mode = pfc->rx_pause_en ? ROC_NIX_FC_RX : ROC_NIX_FC_NONE; + + memset(&pfc_cfg, 0, sizeof(struct roc_nix_pfc_cfg)); + pfc_cfg.mode = mode; + pfc_cfg.tc = pfc->class_en; + rc = roc_nix_pfc_mode_set(nix, &pfc_cfg); exit: return rc; }