From patchwork Fri May 27 03:40:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: fengchengwen X-Patchwork-Id: 111949 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7ACAAA055C; Fri, 27 May 2022 05:47:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 756BB42B6D; Fri, 27 May 2022 05:47:14 +0200 (CEST) Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by mails.dpdk.org (Postfix) with ESMTP id 731B840E78 for ; Fri, 27 May 2022 05:47:09 +0200 (CEST) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.53]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4L8W2Y6HFyzDqKD; Fri, 27 May 2022 11:47:01 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 27 May 2022 11:47:07 +0800 From: Chengwen Feng To: CC: , , Subject: [PATCH 4/4] dma/hisilicon: support vchan-status ops Date: Fri, 27 May 2022 11:40:55 +0800 Message-ID: <20220527034055.33271-5-fengchengwen@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220527034055.33271-1-fengchengwen@huawei.com> References: <20220527034055.33271-1-fengchengwen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds support for vchan-status ops. Signed-off-by: Chengwen Feng --- drivers/dma/hisilicon/hisi_dmadev.c | 30 +++++++++++++++++++++++++++++ drivers/dma/hisilicon/hisi_dmadev.h | 7 ++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c index fbe09284ed..9494b60779 100644 --- a/drivers/dma/hisilicon/hisi_dmadev.c +++ b/drivers/dma/hisilicon/hisi_dmadev.c @@ -461,6 +461,27 @@ hisi_dma_stats_reset(struct rte_dma_dev *dev, uint16_t vchan) return 0; } +static int +hisi_dma_vchan_status(const struct rte_dma_dev *dev, uint16_t vchan, + enum rte_dma_vchan_status *status) +{ + struct hisi_dma_dev *hw = dev->data->dev_private; + uint32_t val; + + RTE_SET_USED(vchan); + + val = hisi_dma_read_queue(hw, HISI_DMA_QUEUE_FSM_REG); + val = FIELD_GET(HISI_DMA_QUEUE_FSM_STS_M, val); + if (val == HISI_DMA_STATE_RUN) + *status = RTE_DMA_VCHAN_ACTIVE; + else if (val == HISI_DMA_STATE_CPL) + *status = RTE_DMA_VCHAN_IDLE; + else + *status = RTE_DMA_VCHAN_HALTED_ERROR; + + return 0; +} + static void hisi_dma_dump_range(struct hisi_dma_dev *hw, FILE *f, uint32_t start, uint32_t end) @@ -816,6 +837,14 @@ hisi_dma_gen_dev_name(const struct rte_pci_device *pci_dev, * dev_stop| | * | v * ------------------ + * | CPL | + * ------------------ + * ^ | + * hardware | | + * completed all| |dev_submit + * descriptors | | + * | | + * ------------------ * | RUN | * ------------------ * @@ -829,6 +858,7 @@ static const struct rte_dma_dev_ops hisi_dmadev_ops = { .vchan_setup = hisi_dma_vchan_setup, .stats_get = hisi_dma_stats_get, .stats_reset = hisi_dma_stats_reset, + .vchan_status = hisi_dma_vchan_status, .dev_dump = hisi_dma_dump, }; diff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h index 90b85322ca..deb1357eea 100644 --- a/drivers/dma/hisilicon/hisi_dmadev.h +++ b/drivers/dma/hisilicon/hisi_dmadev.h @@ -132,11 +132,16 @@ enum { /** * In fact, there are multiple states, but it need to pay attention to - * the following two states for the driver: + * the following three states for the driver: */ enum { HISI_DMA_STATE_IDLE = 0, HISI_DMA_STATE_RUN, + /** + * All of the submitted descriptor are finished, and the queue + * is waiting for new descriptors. + */ + HISI_DMA_STATE_CPL, }; /**