From patchwork Fri May 27 03:40:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: fengchengwen X-Patchwork-Id: 111948 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F5EEA055C; Fri, 27 May 2022 05:47:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7901F4281C; Fri, 27 May 2022 05:47:13 +0200 (CEST) Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mails.dpdk.org (Postfix) with ESMTP id 62D9840E5A for ; Fri, 27 May 2022 05:47:09 +0200 (CEST) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.54]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4L8W0t4j93z1JCRQ; Fri, 27 May 2022 11:45:34 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 27 May 2022 11:47:07 +0800 From: Chengwen Feng To: CC: , , Subject: [PATCH 3/4] dma/hisilicon: enhance robustness of scan CQ Date: Fri, 27 May 2022 11:40:54 +0800 Message-ID: <20220527034055.33271-4-fengchengwen@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220527034055.33271-1-fengchengwen@huawei.com> References: <20220527034055.33271-1-fengchengwen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The CQ (completion queue) descriptors were updated by hardware, and then scanned by driver to retrieve hardware completion status. This patch enhances robustness by following: 1. replace while (true) with a finite loop to avoid potential dead loop. 2. check the csq_head field in CQ descriptor to avoid status array overflows. Fixes: 2db4f0b82360 ("dma/hisilicon: add data path") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng --- drivers/dma/hisilicon/hisi_dmadev.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c index f5c3cd914d..fbe09284ed 100644 --- a/drivers/dma/hisilicon/hisi_dmadev.c +++ b/drivers/dma/hisilicon/hisi_dmadev.c @@ -634,7 +634,7 @@ hisi_dma_scan_cq(struct hisi_dma_dev *hw) uint16_t count = 0; uint64_t misc; - while (true) { + while (count < hw->cq_depth) { cqe = &hw->cqe[cq_head]; misc = cqe->misc; misc = rte_le_to_cpu_64(misc); @@ -642,6 +642,16 @@ hisi_dma_scan_cq(struct hisi_dma_dev *hw) break; csq_head = FIELD_GET(CQE_SQ_HEAD_MASK, misc); + if (unlikely(csq_head > hw->sq_depth_mask)) { + /** + * Defensive programming to prevent overflow of the + * status array indexed by csq_head. Only error logs + * are used for prompting. + */ + HISI_DMA_ERR(hw, "invalid csq_head:%u!\n", csq_head); + count = 0; + break; + } if (unlikely(misc & CQE_STATUS_MASK)) hw->status[csq_head] = FIELD_GET(CQE_STATUS_MASK, misc);