From patchwork Thu Apr 7 09:47:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 109417 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4A831A050B; Thu, 7 Apr 2022 11:47:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1B4004068B; Thu, 7 Apr 2022 11:47:20 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id B197140689 for ; Thu, 7 Apr 2022 11:47:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649324838; x=1680860838; h=from:to:cc:subject:date:message-id; bh=JxpeGpC81dbkTdOHo/djYulk15Oli3170clI1ZCNfDY=; b=G/WuNzsjTvqzhg2QdtsBYBT2CHan15kt4tTQWZAGY93y165STHH6kISj LzmJawQZoybl8yNgvrYelfD+YYTLC08TPuqVr4XpoluP7f4HrKcDxwiSZ tcT5J1tFRBxLH8lJ0OvyUzmPWzV5Pg//KoWmVWEQWvqhE4vpf9fleUQFi AqGq0Oj/VwI18YOYZ8xpQDtTmvG8IFajDsl5CfF0F0UrswJpfxQdkR57F NB9GvdT7d3D0UrydFJsp04Cv3DXCIQfG+NzETkAxRnLSXphP9Q3MzOsX9 ELWJVPV0mCXvDlV4bDSc+AmDgeSTUe6Ukr+QGclp1M/JjCrg87/wA9XE6 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="241209350" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="241209350" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 02:47:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="506085700" Received: from silpixa00400308.ir.intel.com ([10.237.214.95]) by orsmga003.jf.intel.com with ESMTP; 07 Apr 2022 02:47:16 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, roy.fan.zhang@intel.com, Arek Kusztal Subject: [PATCH] crypto/qat: enable asymmetric crypto on gen4 device Date: Thu, 7 Apr 2022 10:47:14 +0100 Message-Id: <20220407094714.19045-1-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit enables asymmetric crypto in generation four devices (4xxx). Signed-off-by: Arek Kusztal Acked-by: Ji, Kai Acked-by: Kai Ji --- doc/guides/cryptodevs/qat.rst | 1 + drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 785e041324..18ad1646a4 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -169,6 +169,7 @@ poll mode crypto driver support for the following hardware accelerator devices: * ``Intel QuickAssist Technology C3xxx`` * ``Intel QuickAssist Technology D15xx`` * ``Intel QuickAssist Technology C4xxx`` +* ``Intel QuickAssist Technology 4xxx`` The QAT ASYM PMD has support for: diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index 3d8b2e377c..a9457d9278 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -375,8 +375,12 @@ RTE_INIT(qat_sym_crypto_gen4_init) RTE_INIT(qat_asym_crypto_gen4_init) { - qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = NULL; - qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = NULL; - qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = NULL; - qat_asym_gen_dev_ops[QAT_GEN4].set_session = NULL; + qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = + &qat_asym_crypto_ops_gen1; + qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = + qat_asym_crypto_cap_get_gen1; + qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = + qat_asym_crypto_feature_flags_get_gen1; + qat_asym_gen_dev_ops[QAT_GEN4].set_session = + qat_asym_crypto_set_session_gen1; }