From patchwork Thu Mar 3 07:00:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 108516 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CDBBBA04A2; Thu, 3 Mar 2022 08:00:57 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6B2244276C; Thu, 3 Mar 2022 08:00:57 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9511B4276B for ; Thu, 3 Mar 2022 08:00:55 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2233tkxS003803; Wed, 2 Mar 2022 23:00:52 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=yfCsA0iowMaxdAGrZZdAcjvm/EGvyvt1EfSFGynPsRk=; b=E4V6FxyEkuzvg29kusEccxnY+p4HGjKqiSQ80kaay97KjPIzXs7aHt0wA+SgvHF8TxiY NP4wmFF4Do2soDncwGLqZI7dmSn4oKpQsOKfJxmYQilD952y1Dz3zCt2qStJi9ixrQDN /nqa1lSqZhSwgiqpFPdUgdZiE8EYfLAVkz//MDX7MmDHMI1MoEsVe46CWG1t2FjEoIXO L6qhFhHYUPBDJy7iBo86Wv2d1QYO8gOTUnsCwziJD1zygCQAKnITz+7e0kENwEhG8BOm cGrp1s2flUmDQIaC/HYwek3X/hXY+NimD97EOJNPPIp1u4CuTSOL/gBi7bf2tF3fSQJJ HA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ej4vfdkae-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Mar 2022 23:00:52 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 2 Mar 2022 23:00:50 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 2 Mar 2022 23:00:50 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 3471F3F70A8; Wed, 2 Mar 2022 23:00:47 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Harman Kalra Subject: [PATCH 2/2] common/cnxk: fix VF data offset Date: Thu, 3 Mar 2022 12:30:42 +0530 Message-ID: <20220303070042.29075-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220303070042.29075-1-ndabilpuram@marvell.com> References: <20220303070042.29075-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: N-54kMdfruG29KgO-Z-fLIY_y7GOtYGn X-Proofpoint-GUID: N-54kMdfruG29KgO-Z-fLIY_y7GOtYGn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-03_02,2022-02-26_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Harman Kalra Data offset should be adjusted for VF to skip extra 8 bytes of timestamp, if its PF has PTP enabled. Fixes: c443e0d326e1 ("common/cnxk: support NIX PTP") Cc: skori@marvell.com Signed-off-by: Harman Kalra Acked-by: Jerin Jacob --- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_ptp.c | 8 ++++++++ drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cnxk_ethdev.c | 4 ++++ 4 files changed, 14 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 5e6eb58..dbb816d 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -864,6 +864,7 @@ int __roc_api roc_nix_ptp_sync_time_adjust(struct roc_nix *roc_nix, int __roc_api roc_nix_ptp_info_cb_register(struct roc_nix *roc_nix, ptp_info_update_t ptp_update); void __roc_api roc_nix_ptp_info_cb_unregister(struct roc_nix *roc_nix); +bool __roc_api roc_nix_ptp_is_enable(struct roc_nix *roc_nix); /* VLAN */ int __roc_api diff --git a/drivers/common/cnxk/roc_nix_ptp.c b/drivers/common/cnxk/roc_nix_ptp.c index 03c4c6e..05e4211 100644 --- a/drivers/common/cnxk/roc_nix_ptp.c +++ b/drivers/common/cnxk/roc_nix_ptp.c @@ -120,3 +120,11 @@ roc_nix_ptp_info_cb_unregister(struct roc_nix *roc_nix) dev->ops->ptp_info_update = NULL; } + +bool +roc_nix_ptp_is_enable(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + return nix->ptp_en; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index d346e6f..2a122e5 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -206,6 +206,7 @@ INTERNAL { roc_nix_ptp_clock_read; roc_nix_ptp_info_cb_register; roc_nix_ptp_info_cb_unregister; + roc_nix_ptp_is_enable; roc_nix_ptp_rx_ena_dis; roc_nix_ptp_sync_time_adjust; roc_nix_ptp_tx_ena_dis; diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index deb95ae..1fa4131 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1123,6 +1123,10 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) goto fail_configure; } + /* Check if ptp is enable in PF owning this VF*/ + if (!roc_nix_is_pf(nix) && (!roc_nix_is_sdp(nix))) + dev->ptp_en = roc_nix_ptp_is_enable(nix); + dev->npc.channel = roc_nix_get_base_chan(nix); nb_rxq = data->nb_rx_queues;