From patchwork Wed Mar 2 12:07:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vamsi Krishna Attunuru X-Patchwork-Id: 108487 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0BC2CA04A4; Wed, 2 Mar 2022 13:07:11 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9BA5442715; Wed, 2 Mar 2022 13:07:10 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 5B7C540141 for ; Wed, 2 Mar 2022 13:07:09 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2228E8C6026488 for ; Wed, 2 Mar 2022 04:07:08 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=wPFr8SSzhj9TAblCZdvfVoTN9GKHhF0QtEnLBfAm7Fk=; b=k8XolWGqrI2shosDA7yMjjuOj7s44pfp45blq7L9J89x7+uztfZu7wyNlpwk7CMtAwJj 5ifcXmu2Inr6zZwDh7jg8oQibjC9/wLsS8IW16CYce3PrfgF4Q8hH6Apd/r49yCTmWpv hlhULaeZzRiKuCGjKR0gJM8Y/Gn4tauRseZ/skow7x8T8Gxa91UFr1A+qXzguSKA3NNU IIqSH1yZp78x1u+2ezDw/GbqdShBLJY0RUWBixVlgOQSEpB5zxxKEJ5BZhIfjcEJFq7K E2pGhEqfL4vb8OPKYpZ9te6OcdtY+a6ehTGoi6vcewzDBURa9/tJcMSexa++kTZT9PWb hQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ej4vf8x8f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Mar 2022 04:07:08 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 2 Mar 2022 04:07:05 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Mar 2022 04:07:05 -0800 Received: from localhost.localdomain (unknown [10.28.48.51]) by maili.marvell.com (Postfix) with ESMTP id 3BE3367387; Wed, 2 Mar 2022 04:07:04 -0800 (PST) From: Vamsi Attunuru To: CC: , , , Srikanth Yalavarthi Subject: [PATCH 1/1] common/cnxk: fix static assertion failure Date: Wed, 2 Mar 2022 17:37:01 +0530 Message-ID: <20220302120701.2749772-1-vattunuru@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: tA2W-nYgSkXaaoh7NetdgB7hEIcWfvG9 X-Proofpoint-GUID: tA2W-nYgSkXaaoh7NetdgB7hEIcWfvG9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-02_06,2022-02-26_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org use dynamically allocated memory for storing soft expiry ring base addresses which fixes the static assertion failure, size of this dynamic allocation depends on RTE_MAX_ETHPORTS which varies based on the build config. Fixes: d26185716d3f ("net/cnxk: support outbound soft expiry notification") Signed-off-by: Vamsi Attunuru Signed-off-by: Srikanth Yalavarthi --- drivers/common/cnxk/roc_nix_inl.c | 23 +++++++++++++---------- drivers/common/cnxk/roc_nix_inl.h | 2 +- drivers/common/cnxk/roc_nix_inl_dev.c | 11 ++++++++++- drivers/common/cnxk/roc_nix_inl_priv.h | 2 +- drivers/common/cnxk/roc_platform.h | 16 ++++++++++++++++ 5 files changed, 41 insertions(+), 13 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 11ed157703..826c6e99c1 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -330,12 +330,13 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) struct dev *dev = &nix->dev; struct msix_offset_rsp *rsp; struct nix_inl_dev *inl_dev; + size_t sa_sz, ring_sz; uint16_t sso_pffunc; uint8_t eng_grpmask; uint64_t blkaddr, i; + uint64_t *ring_base; uint16_t nb_lf; void *sa_base; - size_t sa_sz; int j, rc; void *sa; @@ -468,16 +469,16 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) /* Allocate memory to be used as a ring buffer to poll for * soft expiry event from ucode */ + ring_sz = (ROC_IPSEC_ERR_RING_MAX_ENTRY + 1) * sizeof(uint64_t); + ring_base = inl_dev->sa_soft_exp_ring; for (i = 0; i < nix->outb_se_ring_cnt; i++) { - inl_dev->sa_soft_exp_ring[nix->outb_se_ring_base + i] = - plt_zmalloc((ROC_IPSEC_ERR_RING_MAX_ENTRY + 1) * - sizeof(uint64_t), - 0); - if (!inl_dev->sa_soft_exp_ring[i]) { + ring_base[nix->outb_se_ring_base + i] = + PLT_U64_CAST(plt_zmalloc(ring_sz, 0)); + if (!ring_base[nix->outb_se_ring_base + i]) { plt_err("Couldn't allocate memory for soft exp ring"); while (i--) - plt_free(inl_dev->sa_soft_exp_ring - [nix->outb_se_ring_base + i]); + plt_free(PLT_PTR_CAST( + ring_base[nix->outb_se_ring_base + i])); rc = -ENOMEM; goto lf_fini; } @@ -504,6 +505,7 @@ roc_nix_inl_outb_fini(struct roc_nix *roc_nix) struct idev_cfg *idev = idev_get_cfg(); struct dev *dev = &nix->dev; struct nix_inl_dev *inl_dev; + uint64_t *ring_base; int i, rc, ret = 0; if (!nix->inl_outb_ena) @@ -537,10 +539,11 @@ roc_nix_inl_outb_fini(struct roc_nix *roc_nix) if (idev && idev->nix_inl_dev) { inl_dev = idev->nix_inl_dev; + ring_base = inl_dev->sa_soft_exp_ring; for (i = 0; i < ROC_NIX_INL_MAX_SOFT_EXP_RNGS; i++) { - if (inl_dev->sa_soft_exp_ring[i]) - plt_free(inl_dev->sa_soft_exp_ring[i]); + if (ring_base[i]) + plt_free(PLT_PTR_CAST(ring_base[i])); } } diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 1dc58f2da2..2c2a4d76f2 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -137,7 +137,7 @@ struct roc_nix_inl_dev { bool set_soft_exp_poll; /* End of input parameters */ -#define ROC_NIX_INL_MEM_SZ (2304) +#define ROC_NIX_INL_MEM_SZ (1280) uint8_t reserved[ROC_NIX_INL_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 1cfcdba3f2..5a032aab52 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -653,7 +653,7 @@ inl_outb_soft_exp_poll(struct nix_inl_dev *inl_dev, uint32_t ring_idx) uint32_t port_id; port_id = ring_idx / ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS; - ring_base = inl_dev->sa_soft_exp_ring[ring_idx]; + ring_base = PLT_PTR_CAST(inl_dev->sa_soft_exp_ring[ring_idx]); if (!ring_base) { plt_err("Invalid soft exp ring base"); return; @@ -751,6 +751,14 @@ nix_inl_outb_poll_thread_setup(struct nix_inl_dev *inl_dev) inl_dev->soft_exp_ring_bmap_mem = mem; inl_dev->soft_exp_ring_bmap = bmap; + inl_dev->sa_soft_exp_ring = plt_zmalloc( + ROC_NIX_INL_MAX_SOFT_EXP_RNGS * sizeof(uint64_t), 0); + if (!inl_dev->sa_soft_exp_ring) { + plt_err("soft expiry ring pointer array alloc failed"); + plt_free(mem); + rc = -ENOMEM; + goto exit; + } for (i = 0; i < ROC_NIX_INL_MAX_SOFT_EXP_RNGS; i++) plt_bitmap_clear(inl_dev->soft_exp_ring_bmap, i); @@ -896,6 +904,7 @@ roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev) pthread_join(inl_dev->soft_exp_poll_thread, NULL); plt_bitmap_free(inl_dev->soft_exp_ring_bmap); plt_free(inl_dev->soft_exp_ring_bmap_mem); + plt_free(inl_dev->sa_soft_exp_ring); } /* Flush Inbound CTX cache entries */ diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index da6d6e9b03..0fa5e090d4 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -58,7 +58,7 @@ struct nix_inl_dev { /* OUTB soft expiry poll thread */ pthread_t soft_exp_poll_thread; uint32_t soft_exp_poll_freq; - void *sa_soft_exp_ring[ROC_NIX_INL_MAX_SOFT_EXP_RNGS]; + uint64_t *sa_soft_exp_ring; /* Soft expiry ring bitmap */ struct plt_bitmap *soft_exp_ring_bmap; diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index fa285446bd..267cf6f8fc 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -41,6 +41,7 @@ #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE #define PLT_STD_C11 RTE_STD_C11 #define PLT_PTR_ADD RTE_PTR_ADD +#define PLT_PTR_SUB RTE_PTR_SUB #define PLT_PTR_DIFF RTE_PTR_DIFF #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET @@ -63,6 +64,17 @@ #ifndef PLT_ETHER_ADDR_LEN #define PLT_ETHER_ADDR_LEN RTE_ETHER_ADDR_LEN #endif + +/* Cast to specific datatypes */ +#define PLT_PTR_CAST(val) ((void *)(val)) +#define PLT_U64_CAST(val) ((uint64_t)(val)) +#define PLT_U32_CAST(val) ((uint32_t)(val)) +#define PLT_U16_CAST(val) ((uint16_t)(val)) + +/* Add / Sub pointer with scalar and cast to uint64_t */ +#define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x)) +#define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x)) + /** Divide ceil */ #define PLT_DIV_CEIL(x, y) \ ({ \ @@ -158,6 +170,10 @@ #define plt_write64(val, addr) \ rte_write64_relaxed((val), (volatile void *)(addr)) +#define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr)) +#define plt_write32(val, addr) \ + rte_write32_relaxed((val), (volatile void *)(addr)) + #define plt_wmb() rte_wmb() #define plt_rmb() rte_rmb() #define plt_io_wmb() rte_io_wmb()