From patchwork Wed Mar 2 06:30:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Ke1X" X-Patchwork-Id: 108468 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7626A04A4; Wed, 2 Mar 2022 07:35:48 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1EB0D42701; Wed, 2 Mar 2022 07:35:45 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 20BEF42701 for ; Wed, 2 Mar 2022 07:35:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646202944; x=1677738944; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QVzvC+y505R15yK0zF5756J8D5DIH7fHqVkZj1ZZra8=; b=NegTulCoDiNVYVYWBumrZUiRKAc/odTGs9oOPBi/jw4fJ6Kxq/WwH3y6 bbt8F5tpMCUk0DBj5E9VyMfIrZ1gpFFKxGSu6LlKA98EfZGFjjioR5u9q ZXfOhPlXSyrTCzkdhY+ogZEzyXU5RpxRSQNuQkHRHzLjBXtMtyXTGrHwp FemBMKQNUy4KZfVdnGZMOtn/VHF+6pfXNOacaYP52DItU4mdR5yHYzbc/ 6y+GmoW3oZ744DhOD85Qz37tS4iJmSACgMrSrqIdrEAAhAT5Zmurx4f3f rOrwsLA6elBGDOJH/NdFsujnVEBVZPh9j8l3sjSHsa8xREM5dfB5Tam7v Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10273"; a="236832522" X-IronPort-AV: E=Sophos;i="5.90,148,1643702400"; d="scan'208";a="236832522" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2022 22:35:43 -0800 X-IronPort-AV: E=Sophos;i="5.90,148,1643702400"; d="scan'208";a="641583282" Received: from intel-corei7-64.sh.intel.com (HELO localhost.localdomain) ([10.239.251.104]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2022 22:35:40 -0800 From: Ke Zhang To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Cc: Ke Zhang Subject: [PATCH v6 2/4] net/ice: add support for display/reset stats by DCF Date: Wed, 2 Mar 2022 06:30:50 +0000 Message-Id: <20220302063052.347122-3-ke1x.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302063052.347122-1-ke1x.zhang@intel.com> References: <20220302063052.347122-1-ke1x.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org allow to display/reset VFs stats over VF0. this feature need to update ice kernel driver (newer than v1.8.0) Signed-off-by: Ke Zhang --- drivers/net/ice/ice_dcf_vf_representor.c | 129 +++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/drivers/net/ice/ice_dcf_vf_representor.c b/drivers/net/ice/ice_dcf_vf_representor.c index 781282f68c..765f5d4c95 100644 --- a/drivers/net/ice/ice_dcf_vf_representor.c +++ b/drivers/net/ice/ice_dcf_vf_representor.c @@ -10,6 +10,10 @@ #include "ice_dcf_ethdev.h" #include "ice_rxtx.h" +#define ICE_DCF_REPR_32_BIT_WIDTH (CHAR_BIT * 4) +#define ICE_DCF_REPR_48_BIT_WIDTH (CHAR_BIT * 6) +#define ICE_DCF_REPR_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_REPR_48_BIT_WIDTH, uint64_t) + static __rte_always_inline struct ice_dcf_hw * ice_dcf_vf_repr_hw(struct ice_dcf_vf_repr *repr) { @@ -409,6 +413,129 @@ ice_dcf_vf_repr_vlan_tpid_set(struct rte_eth_dev *dev, return 0; } +static int +ice_dcf_repr_query_stats(struct ice_dcf_hw *hw, + uint16_t vf_id, struct virtchnl_eth_stats *pstats) +{ + struct virtchnl_queue_select q_stats; + struct dcf_virtchnl_cmd args; + int err; + + memset(&q_stats, 0, sizeof(q_stats)); + q_stats.vsi_id = hw->vf_vsi_map[vf_id] & ~VIRTCHNL_DCF_VF_VSI_VALID; + + args.v_op = VIRTCHNL_OP_GET_STATS; + args.req_msg = (uint8_t *)&q_stats; + args.req_msglen = sizeof(q_stats); + args.rsp_msglen = sizeof(struct virtchnl_eth_stats); + args.rsp_msgbuf = (uint8_t *)pstats; + args.rsp_buflen = sizeof(struct virtchnl_eth_stats); + + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (err) { + PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS"); + return err; + } + + return 0; +} + +static int +ice_dcf_vf_repr_stats_reset(struct rte_eth_dev *dev) +{ + struct ice_dcf_vf_repr *repr = dev->data->dev_private; + struct ice_dcf_hw *hw = ice_dcf_vf_repr_hw(repr); + struct virtchnl_eth_stats pstats; + int ret; + + if (hw->resetting) + return 0; + + /* read stat values to clear hardware registers */ + ret = ice_dcf_repr_query_stats(hw, repr->vf_id, &pstats); + if (ret != 0) + return ret; + + /* set stats offset base on current values */ + hw->eth_stats_offset = pstats; + + return 0; +} + +static void +ice_dcf_stat_update_48(uint64_t *offset, uint64_t *stat) +{ + if (*stat >= *offset) + *stat = *stat - *offset; + else + *stat = (uint64_t)((*stat + + ((uint64_t)1 << ICE_DCF_REPR_48_BIT_WIDTH)) - *offset); + + *stat &= ICE_DCF_REPR_48_BIT_MASK; +} + +static void +ice_dcf_stat_update_32(uint64_t *offset, uint64_t *stat) +{ + if (*stat >= *offset) + *stat = (uint64_t)(*stat - *offset); + else + *stat = (uint64_t)((*stat + + ((uint64_t)1 << ICE_DCF_REPR_32_BIT_WIDTH)) - *offset); +} + +static void +ice_dcf_update_stats(struct ice_dcf_hw *hw, struct virtchnl_eth_stats *nes) +{ + struct virtchnl_eth_stats *oes = &hw->eth_stats_offset; + + ice_dcf_stat_update_48(&oes->rx_bytes, &nes->rx_bytes); + ice_dcf_stat_update_48(&oes->rx_unicast, &nes->rx_unicast); + ice_dcf_stat_update_48(&oes->rx_multicast, &nes->rx_multicast); + ice_dcf_stat_update_48(&oes->rx_broadcast, &nes->rx_broadcast); + ice_dcf_stat_update_32(&oes->rx_discards, &nes->rx_discards); + ice_dcf_stat_update_48(&oes->tx_bytes, &nes->tx_bytes); + ice_dcf_stat_update_48(&oes->tx_unicast, &nes->tx_unicast); + ice_dcf_stat_update_48(&oes->tx_multicast, &nes->tx_multicast); + ice_dcf_stat_update_48(&oes->tx_broadcast, &nes->tx_broadcast); + ice_dcf_stat_update_32(&oes->tx_errors, &nes->tx_errors); + ice_dcf_stat_update_32(&oes->tx_discards, &nes->tx_discards); +} + +static int +ice_dcf_vf_repr_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) +{ + struct ice_dcf_vf_repr *repr = dev->data->dev_private; + struct ice_dcf_hw *hw = ice_dcf_vf_repr_hw(repr); + struct virtchnl_eth_stats pstats; + int ret; + + if (hw->resetting) { + PMD_DRV_LOG(ERR, + "The DCF has been reset by PF, please reinit first"); + return -EIO; + } + + ret = ice_dcf_repr_query_stats(hw, repr->vf_id, &pstats); + if (ret == 0) { + uint8_t crc_stats_len = (dev->data->dev_conf.rxmode.offloads & + RTE_ETH_RX_OFFLOAD_KEEP_CRC) ? 0 : + RTE_ETHER_CRC_LEN; + ice_dcf_update_stats(hw, &pstats); + stats->ipackets = pstats.rx_unicast + pstats.rx_multicast + + pstats.rx_broadcast - pstats.rx_discards; + stats->opackets = pstats.tx_broadcast + pstats.tx_multicast + + pstats.tx_unicast; + stats->imissed = pstats.rx_discards; + stats->oerrors = pstats.tx_errors + pstats.tx_discards; + stats->ibytes = pstats.rx_bytes; + stats->ibytes -= stats->ipackets * crc_stats_len; + stats->obytes = pstats.tx_bytes; + } else { + PMD_DRV_LOG(ERR, "Get statistics failed, ret:%d", ret); + } + return ret; +} static const struct eth_dev_ops ice_dcf_vf_repr_dev_ops = { .dev_configure = ice_dcf_vf_repr_dev_configure, .dev_start = ice_dcf_vf_repr_dev_start, @@ -425,6 +552,8 @@ static const struct eth_dev_ops ice_dcf_vf_repr_dev_ops = { .vlan_offload_set = ice_dcf_vf_repr_vlan_offload_set, .vlan_pvid_set = ice_dcf_vf_repr_vlan_pvid_set, .vlan_tpid_set = ice_dcf_vf_repr_vlan_tpid_set, + .stats_reset = ice_dcf_vf_repr_stats_reset, + .stats_get = ice_dcf_vf_repr_stats_get, }; int