From patchwork Fri Feb 18 12:57:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 107808 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 32CC3A0032; Fri, 18 Feb 2022 13:58:00 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1219540150; Fri, 18 Feb 2022 13:58:00 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 4C3DE40141 for ; Fri, 18 Feb 2022 13:57:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645189078; x=1676725078; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=jvLsSTYrYO7SwiEiiZYiTelMf1cQX5/Eo3skKfxQinw=; b=lVixrNR6K+K+OdI8fCKXfa9rYbCPVVLGoCe+p3+15QEarBQOguwR5wzx 6/T8tQdNT1W2QF6/9yPbjQ7pF4Uw3AAFFdJulG1vuFRxNVAlaqLlqFZ1+ 4rKceF/MfEHELc0qBxbv76OoSpZZui9qC2tgehSuCSOTnmLL7O/E+AVhk LxJa9+swFve2BIPxHF7mhJ2EoB6LkC3W0UlbHzIxjjWONlyBt3oMlUhWj 7ibbYWt/l/Qeb2JdoRMGsDabg6kTcn+AZyC8w2ShKadqf65wKTVm36a+k pKayHMCrnhHKmTEOhh/E1ne9nxOa31gnVEP/VikNsLwpb8JrWUF2L41P0 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10261"; a="337564807" X-IronPort-AV: E=Sophos;i="5.88,378,1635231600"; d="scan'208";a="337564807" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2022 04:57:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,378,1635231600"; d="scan'208";a="546272149" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.49]) by orsmga008.jf.intel.com with ESMTP; 18 Feb 2022 04:57:55 -0800 From: Ciara Power To: dev@dpdk.org Cc: roy.fan.zhang@intel.com, gakhil@marvell.com, arkadiuszx.kusztal@intel.com, Ciara Power Subject: [PATCH] crypto: fix asymmetric private session variable size Date: Fri, 18 Feb 2022 12:57:52 +0000 Message-Id: <20220218125752.579335-1-ciara.power@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When creating the asymmetric session mempool, the maximum private session size of all devices is used when creating the mempool object size. The return value for ``rte_cryptodev_asym_get_private_session_size`` is unsigned int, whereas the variable was uint8_t, leading to a possible overflow issue. To fix this, the variable for private session size is now changed to unsigned int to match the function return type. Fixes: 1f1e4b7cbaad ("cryptodev: use single mempool for asymmetric session") Reported-by: Arek Kusztal Signed-off-by: Ciara Power Acked-by: Fan Zhang Acked-by: Arek Kusztal --- lib/cryptodev/rte_cryptodev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/cryptodev/rte_cryptodev.c b/lib/cryptodev/rte_cryptodev.c index 727d271fb9..d262ae6ffa 100644 --- a/lib/cryptodev/rte_cryptodev.c +++ b/lib/cryptodev/rte_cryptodev.c @@ -1810,7 +1810,8 @@ rte_cryptodev_asym_session_pool_create(const char *name, uint32_t nb_elts, struct rte_mempool *mp; struct rte_cryptodev_asym_session_pool_private_data *pool_priv; uint32_t obj_sz, obj_sz_aligned; - uint8_t dev_id, priv_sz, max_priv_sz = 0; + uint8_t dev_id; + unsigned int priv_sz, max_priv_sz = 0; for (dev_id = 0; dev_id < RTE_CRYPTO_MAX_DEVS; dev_id++) if (rte_cryptodev_is_valid_dev(dev_id)) {