From patchwork Mon Dec 13 21:14:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 105119 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 398C9A034D; Mon, 13 Dec 2021 22:15:35 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C58741144; Mon, 13 Dec 2021 22:15:30 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9163E410FD for ; Mon, 13 Dec 2021 22:15:27 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BDElFcF030003 for ; Mon, 13 Dec 2021 13:15:26 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=0tbKQY3YnFpiYokYygYzVG5IbfhXbHrmFt3guMChWEE=; b=aX17xC6O1O/MqK003n5d6q37EA9ybiHn/XTKY3+G0EZHleM+EdaHAvRorZyQH2xtTrGo Wb69jhmyR6cEa5EALgR5NxSsWqkrUQSI9pQ6bYqK8LrwAUNmQMFpQ7ei6F2SmLKOjIlq WKTpoEaxAXy5CFo6DDFqEATpKvVSf47MnnEbBvfJH8DlOBFbkog/HeoFFF1dLvpq0vLP ra3NHT1yKPI5aiel1X3eAf2rxwjJN9+EYfCps/35MllVGqd3ea4v55FC9owoyH2mE8uZ 3NS28WNQHOafkzUm2LmxfesnVyikx2eo5LcPgG3AQefZowz8LcVjUd0iWlgODuyNm5ba LQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cx88ahnmc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 13 Dec 2021 13:15:26 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Dec 2021 13:15:25 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Dec 2021 13:15:25 -0800 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 4859B3F704A; Mon, 13 Dec 2021 13:15:22 -0800 (PST) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh , Shijith Thotton CC: Subject: [PATCH 2/4] event/cnxk: store and reuse workslot status Date: Tue, 14 Dec 2021 02:44:22 +0530 Message-ID: <20211213211425.6332-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211213211425.6332-1-pbhagavatula@marvell.com> References: <20211213211425.6332-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: lFcT46mnYw99gwEZ1wwjHuPKvvxlAYtM X-Proofpoint-ORIG-GUID: lFcT46mnYw99gwEZ1wwjHuPKvvxlAYtM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-13_10,2021-12-13_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Store and reuse workslot status for TT, GRP and HEAD status instead of reading from GWC as reading from GWC imposes additional latency. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/roc_sso.h | 11 ++++++----- drivers/event/cnxk/cn10k_worker.h | 17 ++++++++++------- drivers/event/cnxk/cnxk_eventdev.h | 2 ++ drivers/event/cnxk/cnxk_worker.h | 11 +++++++---- drivers/net/cnxk/cn10k_tx.h | 12 ++++++------ 5 files changed, 31 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index 27d49c6c68..9c594f5c1c 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -54,12 +54,12 @@ struct roc_sso { uint8_t reserved[ROC_SSO_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; -static __plt_always_inline void +static __plt_always_inline uint64_t roc_sso_hws_head_wait(uintptr_t tag_op) { -#ifdef RTE_ARCH_ARM64 uint64_t tag; +#ifdef RTE_ARCH_ARM64 asm volatile(PLT_CPU_FEATURE_PREAMBLE " ldr %[tag], [%[tag_op]] \n" " tbnz %[tag], 35, done%= \n" @@ -71,10 +71,11 @@ roc_sso_hws_head_wait(uintptr_t tag_op) : [tag] "=&r"(tag) : [tag_op] "r"(tag_op)); #else - /* Wait for the SWTAG/SWTAG_FULL operation */ - while (!(plt_read64(tag_op) & BIT_ULL(35))) - ; + do { + tag = plt_read64(tag_op); + } while (!(tag & BIT_ULL(35))); #endif + return tag; } /* SSO device initialization */ diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index e80e4fb895..65602a632e 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -40,8 +40,7 @@ cn10k_sso_hws_fwd_swtag(struct cn10k_sso_hws *ws, const struct rte_event *ev) { const uint32_t tag = (uint32_t)ev->event; const uint8_t new_tt = ev->sched_type; - const uint8_t cur_tt = - CNXK_TT_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_WQE0)); + const uint8_t cur_tt = CNXK_TT_FROM_TAG(ws->gw_rdata); /* CNXK model * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED @@ -81,7 +80,7 @@ cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws, const uint8_t grp = ev->queue_id; /* Group hasn't changed, Use SWTAG to forward the event */ - if (CNXK_GRP_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_WQE0)) == grp) + if (CNXK_GRP_FROM_TAG(ws->gw_rdata) == grp) cn10k_sso_hws_fwd_swtag(ws, ev); else /* @@ -211,6 +210,7 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev, } while (gw.u64[0] & BIT_ULL(63)); mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf)); #endif + ws->gw_rdata = gw.u64[0]; gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 | (gw.u64[0] & (0x3FFull << 36)) << 4 | (gw.u64[0] & 0xffffffff); @@ -406,7 +406,8 @@ NIX_RX_FASTPATH_MODES RTE_SET_USED(timeout_ticks); \ if (ws->swtag_req) { \ ws->swtag_req = 0; \ - cnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0); \ + ws->gw_rdata = cnxk_sso_hws_swtag_wait( \ + ws->base + SSOW_LF_GWS_WQE0); \ return 1; \ } \ return cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \ @@ -426,7 +427,8 @@ NIX_RX_FASTPATH_MODES \ if (ws->swtag_req) { \ ws->swtag_req = 0; \ - cnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0); \ + ws->gw_rdata = cnxk_sso_hws_swtag_wait( \ + ws->base + SSOW_LF_GWS_WQE0); \ return ret; \ } \ ret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \ @@ -509,8 +511,9 @@ cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd, else pa = txq->io_addr | ((segdw - 1) << 4); - if (!sched_type) - roc_sso_hws_head_wait(ws->base + SSOW_LF_GWS_TAG); + if (!CNXK_TAG_IS_HEAD(ws->gw_rdata) && !sched_type) + ws->gw_rdata = + roc_sso_hws_head_wait(ws->base + SSOW_LF_GWS_TAG); roc_lmt_submit_steorl(lmt_id, pa); } diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index b26df58588..ab58508590 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -47,6 +47,7 @@ #define CNXK_CLR_SUB_EVENT(x) (~(0xffu << 20) & x) #define CNXK_GRP_FROM_TAG(x) (((x) >> 36) & 0x3ff) #define CNXK_SWTAG_PEND(x) (BIT_ULL(62) & x) +#define CNXK_TAG_IS_HEAD(x) (BIT_ULL(35) & x) #define CN9K_SSOW_GET_BASE_ADDR(_GW) ((_GW)-SSOW_LF_GWS_OP_GET_WORK0) @@ -123,6 +124,7 @@ struct cnxk_sso_evdev { struct cn10k_sso_hws { uint64_t base; + uint64_t gw_rdata; /* PTP timestamp */ struct cnxk_timesync_info *tstamp; void *lookup_mem; diff --git a/drivers/event/cnxk/cnxk_worker.h b/drivers/event/cnxk/cnxk_worker.h index 9f9ceab8a1..7de03f3fbb 100644 --- a/drivers/event/cnxk/cnxk_worker.h +++ b/drivers/event/cnxk/cnxk_worker.h @@ -52,11 +52,11 @@ cnxk_sso_hws_swtag_flush(uint64_t tag_op, uint64_t flush_op) plt_write64(0, flush_op); } -static __rte_always_inline void +static __rte_always_inline uint64_t cnxk_sso_hws_swtag_wait(uintptr_t tag_op) { -#ifdef RTE_ARCH_ARM64 uint64_t swtp; +#ifdef RTE_ARCH_ARM64 asm volatile(PLT_CPU_FEATURE_PREAMBLE " ldr %[swtb], [%[swtp_loc]] \n" @@ -70,9 +70,12 @@ cnxk_sso_hws_swtag_wait(uintptr_t tag_op) : [swtp_loc] "r"(tag_op)); #else /* Wait for the SWTAG/SWTAG_FULL operation */ - while (plt_read64(tag_op) & BIT_ULL(62)) - ; + do { + swtp = plt_read64(tag_op); + } while (swtp & BIT_ULL(62)); #endif + + return swtp; } #endif diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index b3034c72cb..8b2f1c868e 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -905,8 +905,8 @@ cn10k_nix_xmit_pkts(void *tx_queue, uint64_t *ws, struct rte_mbuf **tx_pkts, lnum++; } - if (flags & NIX_TX_VWQE_F) - roc_sso_hws_head_wait(ws[0]); + if ((flags & NIX_TX_VWQE_F) && !(ws[1] & BIT_ULL(35))) + ws[1] = roc_sso_hws_head_wait(ws[0]); left -= burst; tx_pkts += burst; @@ -1041,8 +1041,8 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, uint64_t *ws, } } - if (flags & NIX_TX_VWQE_F) - roc_sso_hws_head_wait(ws[0]); + if ((flags & NIX_TX_VWQE_F) && !(ws[1] & BIT_ULL(35))) + ws[1] = roc_sso_hws_head_wait(ws[0]); left -= burst; tx_pkts += burst; @@ -2582,8 +2582,8 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws, if (flags & (NIX_TX_MULTI_SEG_F | NIX_TX_OFFLOAD_SECURITY_F)) wd.data[0] >>= 16; - if (flags & NIX_TX_VWQE_F) - roc_sso_hws_head_wait(ws[0]); + if ((flags & NIX_TX_VWQE_F) && !(ws[1] & BIT_ULL(35))) + ws[1] = roc_sso_hws_head_wait(ws[0]); left -= burst;