From patchwork Mon Dec 13 20:56:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 105117 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C9F49A00C3; Mon, 13 Dec 2021 21:56:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9059A406A2; Mon, 13 Dec 2021 21:56:44 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 2DD9240042 for ; Mon, 13 Dec 2021 21:56:42 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BDElJaH030051 for ; Mon, 13 Dec 2021 12:56:41 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=NPsLO+vE97WBEIMdMU6389p0bD9DXs7F90Og6gMLrUg=; b=ZifAXobfxMVpdKtT7lWPK9//p/tq9EYPojAIBJRvCvtYlKUbgZ4nPYoIGsPQaxHq7M0c x9YcyA4bELHlTIpZ7LPxryV74Hk1T3PSLyEf0ziIYn7oviOxyzRSvpQk0xsRNQmVW5qw YZU7Yfr3qlQMVyi4jD6VjFjz38INZvBCY+ye/lwE6mFXUh3NBozONrR7LpPEbrPnD3b/ fSl/PHkp11Sqmosl8pTXy3r5QUHPL9l1Y/PDE6Rh72vb9aqYcxyC+RikfaeZjXcVeGz+ z3e0bp1xtyFkzwEChCwvWCNL7iAk0uKvfR0u3pXyKK8EA8Eu80DTJG6y0TvX9fcio2jk ug== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cx88ahk4r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 13 Dec 2021 12:56:41 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Dec 2021 12:56:39 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Dec 2021 12:56:39 -0800 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 900F43F7078; Mon, 13 Dec 2021 12:56:37 -0800 (PST) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Subject: [PATCH] common/cnxk: use XAQ create API for inline device Date: Tue, 14 Dec 2021 02:26:33 +0530 Message-ID: <20211213205633.5724-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Proofpoint-GUID: FJoHasMdRiM7odUUHYnkKNu1jSkPRL_q X-Proofpoint-ORIG-GUID: FJoHasMdRiM7odUUHYnkKNu1jSkPRL_q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-13_10,2021-12-13_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Use the XAQ aura create and free API while initializing the inline device. Signed-off-by: Pavan Nikhilesh Acked-by: Jerin Jacob --- drivers/common/cnxk/roc_nix_debug.c | 4 +- drivers/common/cnxk/roc_nix_inl_dev.c | 53 ++++++-------------------- drivers/common/cnxk/roc_nix_inl_priv.h | 3 +- 3 files changed, 15 insertions(+), 45 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c index 266935a6c5..5886650d6e 100644 --- a/drivers/common/cnxk/roc_nix_debug.c +++ b/drivers/common/cnxk/roc_nix_debug.c @@ -1257,8 +1257,8 @@ roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev) nix_dump(" \txaq_buf_size = %u", inl_dev->xaq_buf_size); nix_dump(" \txae_waes = %u", inl_dev->xae_waes); nix_dump(" \tiue = %u", inl_dev->iue); - nix_dump(" \txaq_aura = 0x%" PRIx64, inl_dev->xaq_aura); - nix_dump(" \txaq_mem = 0x%p", inl_dev->xaq_mem); + nix_dump(" \txaq_aura = 0x%" PRIx64, inl_dev->xaq.aura_handle); + nix_dump(" \txaq_mem = 0x%p", inl_dev->xaq.mem); nix_dump(" \tinl_dev_rq:"); roc_nix_rq_dump(&inl_dev->rq); diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 10912a6c93..dd93765a2b 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -5,8 +5,6 @@ #include "roc_api.h" #include "roc_priv.h" -#define XAQ_CACHE_CNT 0x7 - /* Default Rx Config for Inline NIX LF */ #define NIX_INL_LF_RX_CFG \ (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR | \ @@ -220,10 +218,8 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev) { struct sso_lf_alloc_rsp *sso_rsp; struct dev *dev = &inl_dev->dev; - uint32_t xaq_cnt, count, aura; uint16_t hwgrp[1] = {0}; - struct npa_pool_s pool; - uintptr_t iova; + uint32_t xae_cnt; int rc; /* Alloc SSOW LF */ @@ -244,41 +240,17 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev) inl_dev->xae_waes = sso_rsp->xaq_wq_entries; inl_dev->iue = sso_rsp->in_unit_entries; - /* Create XAQ pool */ - xaq_cnt = XAQ_CACHE_CNT; - xaq_cnt += inl_dev->iue / inl_dev->xae_waes; - plt_sso_dbg("Configuring %d xaq buffers", xaq_cnt); - - inl_dev->xaq_mem = plt_zmalloc(inl_dev->xaq_buf_size * xaq_cnt, - inl_dev->xaq_buf_size); - if (!inl_dev->xaq_mem) { - rc = NIX_ERR_NO_MEM; - plt_err("Failed to alloc xaq buf mem"); - goto free_sso; - } - - memset(&pool, 0, sizeof(struct npa_pool_s)); - pool.nat_align = 1; - rc = roc_npa_pool_create(&inl_dev->xaq_aura, inl_dev->xaq_buf_size, - xaq_cnt, NULL, &pool); + xae_cnt = inl_dev->iue; + rc = sso_hwgrp_init_xaq_aura(dev, &inl_dev->xaq, xae_cnt, + inl_dev->xae_waes, inl_dev->xaq_buf_size, + 1); if (rc) { - plt_err("Failed to alloc aura for XAQ, rc=%d", rc); - goto free_mem; - } - - /* Fill the XAQ buffers */ - iova = (uint64_t)inl_dev->xaq_mem; - for (count = 0; count < xaq_cnt; count++) { - roc_npa_aura_op_free(inl_dev->xaq_aura, 0, iova); - iova += inl_dev->xaq_buf_size; + plt_err("Failed to alloc SSO XAQ aura, rc=%d", rc); + goto free_sso; } - roc_npa_aura_op_range_set(inl_dev->xaq_aura, (uint64_t)inl_dev->xaq_mem, - iova); - - aura = roc_npa_aura_handle_to_aura(inl_dev->xaq_aura); /* Setup xaq for hwgrps */ - rc = sso_hwgrp_alloc_xaq(dev, aura, 1); + rc = sso_hwgrp_alloc_xaq(dev, inl_dev->xaq.aura_handle, 1); if (rc) { plt_err("Failed to setup hwgrp xaq aura, rc=%d", rc); goto destroy_pool; @@ -302,11 +274,7 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev) release_xaq: sso_hwgrp_release_xaq(&inl_dev->dev, 1); destroy_pool: - roc_npa_pool_destroy(inl_dev->xaq_aura); - inl_dev->xaq_aura = 0; -free_mem: - plt_free(inl_dev->xaq_mem); - inl_dev->xaq_mem = NULL; + sso_hwgrp_free_xaq_aura(dev, &inl_dev->xaq, 0); free_sso: sso_lf_free(dev, SSO_LF_TYPE_HWGRP, 1); free_ssow: @@ -335,6 +303,9 @@ nix_inl_sso_release(struct nix_inl_dev *inl_dev) sso_lf_free(&inl_dev->dev, SSO_LF_TYPE_HWS, 1); sso_lf_free(&inl_dev->dev, SSO_LF_TYPE_HWGRP, 1); + /* Free the XAQ aura */ + sso_hwgrp_free_xaq_aura(&inl_dev->dev, &inl_dev->xaq, 0); + return 0; } diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index be53a3fa81..2cdab6dc7a 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -27,8 +27,7 @@ struct nix_inl_dev { uint32_t xaq_buf_size; uint32_t xae_waes; uint32_t iue; - uint64_t xaq_aura; - void *xaq_mem; + struct roc_sso_xaq_data xaq; roc_nix_inl_sso_work_cb_t work_cb; void *cb_args;