From patchwork Thu Nov 18 09:39:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Zhang X-Patchwork-Id: 104506 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 541F6A0C41; Thu, 18 Nov 2021 10:39:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DBB6540687; Thu, 18 Nov 2021 10:39:43 +0100 (CET) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 5F4CE40395 for ; Thu, 18 Nov 2021 10:39:41 +0100 (CET) X-IronPort-AV: E=McAfee;i="6200,9189,10171"; a="221365526" X-IronPort-AV: E=Sophos;i="5.87,244,1631602800"; d="scan'208";a="221365526" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2021 01:39:40 -0800 X-IronPort-AV: E=Sophos;i="5.87,244,1631602800"; d="scan'208";a="646435378" Received: from intel-odc-server03.cd.intel.com ([10.240.178.134]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2021 01:39:37 -0800 From: Robin Zhang To: dev@dpdk.org Cc: beilei.xing@intel.com, qi.z.zhang@intel.com, junfeng.guo@intel.com, stevex.yang@intel.com, Robin Zhang Subject: [PATCH] net/i40e: add outer VLAN processing Date: Thu, 18 Nov 2021 09:39:19 +0000 Message-Id: <20211118093919.7995-1-robinx.zhang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Outer VLAN processing is supported after firmware v8.4, kernel driver also change the default behavior to support this feature. To align with kernel driver, add support for outer VLAN processing in DPDK. This will not impact on an old firmware. Signed-off-by: Robin Zhang --- drivers/net/i40e/i40e_ethdev.c | 58 +++++++++++++++++++++++++++++++--- drivers/net/i40e/i40e_ethdev.h | 3 ++ 2 files changed, 56 insertions(+), 5 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 344cbd25d3..6e6c0d51ac 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -2591,11 +2591,31 @@ i40e_dev_close(struct rte_eth_dev *dev) int ret; uint8_t aq_fail = 0; int retries = 0; + int mask = 0; + struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; PMD_INIT_FUNC_TRACE(); if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; + /* + * To avoid global register conflict with kernel driver, need set + * switch configuration back to default, disable double vlan and + * clear the VLAN filters when dev close. + */ + if (pf->is_outer_vlan_processing && + (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)) { + mask = RTE_ETH_VLAN_EXTEND_MASK; + rxmode->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; + + if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { + mask |= RTE_ETH_VLAN_FILTER_MASK; + rxmode->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_FILTER; + } + + i40e_vlan_offload_set(dev, mask); + } + ret = rte_eth_switch_domain_free(pf->switch_domain_id); if (ret) PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret); @@ -3918,6 +3938,7 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev, int qinq = dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; int ret = 0; + u16 sw_flags = 0, valid_flags = 0; if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER && vlan_type != RTE_ETH_VLAN_TYPE_OUTER) || @@ -3935,15 +3956,28 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev, /* 802.1ad frames ability is added in NVM API 1.7*/ if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { if (qinq) { + if (pf->is_outer_vlan_processing) { + sw_flags = I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN; + valid_flags = I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN; + } if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) hw->first_tag = rte_cpu_to_le_16(tpid); else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) hw->second_tag = rte_cpu_to_le_16(tpid); } else { - if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) - hw->second_tag = rte_cpu_to_le_16(tpid); + if (pf->is_outer_vlan_processing) { + sw_flags = 0; + valid_flags = I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN; + } + if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) { + if (pf->is_outer_vlan_processing) + hw->first_tag = rte_cpu_to_le_16(tpid); + else + hw->second_tag = rte_cpu_to_le_16(tpid); + } } - ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL); + ret = i40e_aq_set_switch_config(hw, sw_flags, + valid_flags, 0, NULL); if (ret != I40E_SUCCESS) { PMD_DRV_LOG(ERR, "Set switch config failed aq_err: %d", @@ -4022,9 +4056,12 @@ i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) RTE_ETHER_TYPE_VLAN); i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER, RTE_ETHER_TYPE_VLAN); - } - else + } else { + if (pf->is_outer_vlan_processing) + i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER, + RTE_ETHER_TYPE_QINQ); i40e_vsi_config_double_vlan(vsi, FALSE); + } } if (mask & RTE_ETH_QINQ_STRIP_MASK) { @@ -4854,6 +4891,17 @@ i40e_pf_parameter_init(struct rte_eth_dev *dev) return -EINVAL; } + /** + * Enable outer VLAN processing if firmware version is greater + * than v8.3 + */ + if (hw->aq.fw_maj_ver > 8 || + (hw->aq.fw_maj_ver == 8 && hw->aq.fw_min_ver > 3)) { + pf->is_outer_vlan_processing = true; + } else { + pf->is_outer_vlan_processing = false; + } + return 0; } diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index d8042abbd9..e62e2fba4f 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -1190,6 +1190,9 @@ struct i40e_pf { /* Switch Domain Id */ uint16_t switch_domain_id; + /* The enable flag for outer VLAN processing */ + bool is_outer_vlan_processing; + struct i40e_vf_msg_cfg vf_msg_cfg; uint64_t prev_rx_bytes; uint64_t prev_tx_bytes;