diff mbox series

[1/2] compress/mlx5: fix level configuration in compress

Message ID 20211026015242.21156-2-rzidane@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series fix level configuration in compress |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Raja Zidane Oct. 26, 2021, 1:52 a.m. UTC 
  The mlx5 compress PMD uses HW acceleration for the compress operations.
The mlx5 HW device has no level style mode, which does a tradeoff between
throughput and compression ratio, unlike SW drivers where the CPU is doing
the compress, and more CPU effort can cause a better compression ratio.
The mlx5 driver wrongly defined the Huffman block size configuration
according to the level that doesn't fill the level API requirement for
the tradeoff.

Remove the effect of the level configuration in compress operation.

Fixes: 237aad88245b ("compress/mlx5: fix compression level translation")
Fixes: 39a2c8715f8f ("compress/mlx5: add transformation operations")
Cc: stable@dpdk.org

Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/compress/mlx5/mlx5_compress.c | 18 +++---------------
 1 file changed, 3 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index c4081c5f7d..9adc0e41e0 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -343,21 +343,9 @@  mlx5_compress_xform_create(struct rte_compressdev *dev,
 			xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 					 MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 						WQE_GGA_COMP_WIN_SIZE_OFFSET;
-			switch (xform->compress.level) {
-			case RTE_COMP_LEVEL_PMD_DEFAULT:
-				size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
-				break;
-			case RTE_COMP_LEVEL_MAX:
-				size = priv->min_block_size;
-				break;
-			default:
-				size = RTE_MAX(MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX
-					+ 1 - xform->compress.level,
-					priv->min_block_size);
-			}
-			xfrm->gga_ctrl1 += RTE_MIN(size,
-					    MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
-						 WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
+			size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
+			xfrm->gga_ctrl1 += size <<
+						WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 			xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 							WQE_CSEG_OPC_MOD_OFFSET;
 			size = xform->compress.deflate.huffman ==