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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT025.mail.protection.outlook.com (10.13.172.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4587.18 via Frontend Transport; Tue, 12 Oct 2021 12:46:43 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 12 Oct 2021 12:46:35 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 12 Oct 2021 15:45:47 +0300 Message-ID: <20211012124554.21296-7-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20211012124554.21296-1-talshn@nvidia.com> References: <20211012124554.21296-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2b91557d-054f-4eb0-43e7-08d98d7e5815 X-MS-TrafficTypeDiagnostic: MW3PR12MB4395: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:741; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(7696005)(36860700001)(7636003)(316002)(6666004)(186003)(336012)(356005)(70206006)(508600001)(1076003)(2906002)(107886003)(70586007)(4326008)(54906003)(83380400001)(26005)(5660300002)(55016002)(36756003)(6916009)(6286002)(47076005)(8936002)(82310400003)(2616005)(8676002)(426003)(86362001)(16526019); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2021 12:46:43.1640 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b91557d-054f-4eb0-43e7-08d98d7e5815 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4395 Subject: [dpdk-dev] [PATCH v2 06/13] net/mlx5: query tunneling support on Windows X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Query tunneling supported on the NIC. Save the offloads values in a config parameter. This is needed for the following TSO support: DEV_TX_OFFLOAD_VXLAN_TNL_TSO DEV_TX_OFFLOAD_GRE_TNL_TSO DEV_TX_OFFLOAD_GENEVE_TNL_TSO Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad Tested-by: Idan Hackmon --- drivers/net/mlx5/mlx5.c | 14 ++++++++++++++ drivers/net/mlx5/mlx5.h | 2 ++ drivers/net/mlx5/windows/mlx5_os.c | 20 ++++++++++++++++++-- 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index add07db755..a957bc9938 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -966,6 +966,20 @@ mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr) return sw_parsing_offloads; } +uint32_t +mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr) +{ + uint32_t tn_offloads = 0; + + if (attr->tunnel_stateless_vxlan) + tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP; + if (attr->tunnel_stateless_gre) + tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP; + if (attr->tunnel_stateless_geneve_rx) + tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP; + return tn_offloads; +} + /* * Allocate Rx and Tx UARs in robust fashion. * This routine handles the following UAR allocation issues: diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 58f12cd75c..0dbb9aacb8 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1830,5 +1830,7 @@ int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, struct mlx5_aso_ct_action *ct); uint32_t mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr); +uint32_t +mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr); #endif /* RTE_PMD_MLX5_H_ */ diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 1e258e044e..fab7d7efcb 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -171,6 +171,8 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) } device_attr->sw_parsing_offloads = mlx5_get_supported_sw_parsing_offloads(&hca_attr); + device_attr->tunnel_offloads_caps = + mlx5_get_supported_tunneling_offloads(&hca_attr); pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg); if (pv_iseg == NULL) { DRV_LOG(ERR, "Failed to get device hca_iseg"); @@ -402,8 +404,22 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, sh->device_attr.max_rwq_indirection_table_size; cqe_comp = 0; config->cqe_comp = cqe_comp; - DRV_LOG(DEBUG, "tunnel offloading is not supported"); - config->tunnel_en = 0; + config->tunnel_en = device_attr.tunnel_offloads_caps & + (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP | + MLX5_TUNNELED_OFFLOADS_GRE_CAP | + MLX5_TUNNELED_OFFLOADS_GENEVE_CAP); + if (config->tunnel_en) { + DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s", + config->tunnel_en & + MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "", + config->tunnel_en & + MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "", + config->tunnel_en & + MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : "" + ); + } else { + DRV_LOG(DEBUG, "tunnel offloading is not supported"); + } DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported"); config->mpls_en = 0; /* Allocate private eth device data. */