From patchwork Sat Oct 9 01:39:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Zhang X-Patchwork-Id: 100877 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C182A034F; Sat, 9 Oct 2021 03:54:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7D631410F2; Sat, 9 Oct 2021 03:54:22 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 82CB040F35 for ; Sat, 9 Oct 2021 03:54:19 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10131"; a="206739834" X-IronPort-AV: E=Sophos;i="5.85,358,1624345200"; d="scan'208";a="206739834" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 18:54:19 -0700 X-IronPort-AV: E=Sophos;i="5.85,358,1624345200"; d="scan'208";a="624917051" Received: from unknown (HELO intel-npg-odc-srv03.cd.intel.com) ([10.240.178.145]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 18:54:15 -0700 From: Robin Zhang To: dev@dpdk.org Cc: beilei.xing@intel.com, qi.z.zhang@intel.com, helin.zhang@intel.com, jingjing.wu@intel.com, remy.horton@intel.com, jijiang.liu@intel.com, jing.d.chen@intel.com, cunming.liang@intel.com, wenzhuo.lu@intel.com, junfeng.guo@intel.com, stevex.yang@intel.com, Robin Zhang , Stanislaw Grzeszczak Date: Sat, 9 Oct 2021 01:39:41 +0000 Message-Id: <20211009013956.70937-3-robinx.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211009013956.70937-1-robinx.zhang@intel.com> References: <20210618063851.3694702-1-robinx.zhang@intel.com> <20211009013956.70937-1-robinx.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 02/17] net/i40e/base: add Min SRev for 4 more X722 modules X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Some customers want to downgrade to an earlier FW security revision, this already implemented by FW so that customers can have more control over the security revisions they can use. FW also implemented a mechanism via NVMupdate to allow the users to accept or not a baseline Min SRev version that will limit the secure version rollback only down to that level. This commit increments X722 API version and adds new minimal rollback revision that related to the extended implementation of Security Revision Opt-In for 4 more X722 modules. These definitions are not using by DPDK now, the purpose of this commit is sync with latest share code. Signed-off-by: Stanislaw Grzeszczak Signed-off-by: Robin Zhang --- drivers/net/i40e/base/i40e_adminq_cmd.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h index 2ca41db5d3..a96527f31c 100644 --- a/drivers/net/i40e/base/i40e_adminq_cmd.h +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h @@ -12,7 +12,7 @@ */ #define I40E_FW_API_VERSION_MAJOR 0x0001 -#define I40E_FW_API_VERSION_MINOR_X722 0x000B +#define I40E_FW_API_VERSION_MINOR_X722 0x000C #define I40E_FW_API_VERSION_MINOR_X710 0x000C #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ @@ -2425,11 +2425,15 @@ struct i40e_aqc_rollback_revision_update { u8 optin_mode; /* bool */ #define I40E_AQ_RREV_OPTION_MODE 0x01 u8 module_selected; -#define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0 -#define I40E_AQ_RREV_MODULE_PHY_ANALOG 1 -#define I40E_AQ_RREV_MODULE_OPTION_ROM 2 -#define I40E_AQ_RREV_MODULE_EMP_IMAGE 3 -#define I40E_AQ_RREV_MODULE_PE_IMAGE 4 +#define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0 +#define I40E_AQ_RREV_MODULE_PHY_ANALOG 1 +#define I40E_AQ_RREV_MODULE_OPTION_ROM 2 +#define I40E_AQ_RREV_MODULE_EMP_IMAGE 3 +#define I40E_AQ_RREV_MODULE_PE_IMAGE 4 +#define I40E_AQ_RREV_MODULE_PHY_PLL_O_CONFIGURATION 5 +#define I40E_AQ_RREV_MODULE_PHY_0_CONFIGURATION 6 +#define I40E_AQ_RREV_MODULE_PHY_PLL_1_CONFIGURATION 7 +#define I40E_AQ_RREV_MODULE_PHY_1_CONFIGURATION 8 u8 reserved1[2]; u32 min_rrev; u8 reserved2[8];