From patchwork Thu Oct 7 18:43:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srikanth Kaka X-Patchwork-Id: 100792 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D82DCA034F; Fri, 8 Oct 2021 12:58:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C083411BF; Fri, 8 Oct 2021 12:56:25 +0200 (CEST) Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) by mails.dpdk.org (Postfix) with ESMTP id AAEA1411E0 for ; Thu, 7 Oct 2021 20:45:19 +0200 (CEST) Received: by mail-pl1-f178.google.com with SMTP id w11so4460812plz.13 for ; Thu, 07 Oct 2021 11:45:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oneconvergence.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S9Cn4hcXEh6D9+/Yvdeg18iBAGpkDiqGaTyozeG3jNU=; b=Sj3j7z0f/Ek112PnGN/AGMduWpJxqoKFcQxTOF3q7R3p0sGXh86gcfamS9mqgmp1kg r8PSrefksltguYinretWTQHtKIgoPeA09Pu1K1JCUj4Pj6+0enVl+BnwBYGnYP9olhIC 3zMghKbY9UQSJrP0y/7aigcu633Fvh8hQdZnY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S9Cn4hcXEh6D9+/Yvdeg18iBAGpkDiqGaTyozeG3jNU=; b=NGQPV3rpP1efTRCVumzgLPhLe94BK/2lhkc1zeSal9PA0E8XgojnfBzQQYpxQIkuus Ps9GRL8sHoohQrgligvAKnIXeXl9fiuniJMqMC1Q5AV0BdaTM4Xla6Ozq9eBEMMO02/c wdz9SI94LmQBDeaKSebNe8kHx8/Gksc1sALX9MQV90KJ4hr+dI61NkVxfCGUwDJqxuD5 oMGxXgajygFdDYUNL7t1xagNUbI9xTFGuQFxLLXGs0WNctqBj9us+A7xmy5ovkp+Jco8 rpCitcvkEuCR1kuV59q0fCc4t9f8SZdIFBg+so2MCN18DcAXUzbS1U15j4nTsje6ASaq p8hA== X-Gm-Message-State: AOAM531hCRv6sbnRdCHMRuOyKkFkT3D96k4pKBBASelTd3fXDXsu7d8x qyUS26Bd/Kcs10ZzGo7uoOofww== X-Google-Smtp-Source: ABdhPJy6diteasxIG6ytMJSjflnmk2mcqUEo7liWGxjHiTTC9ShQatxMIdkfxWWR9Gyoj1GaUnQkGQ== X-Received: by 2002:a17:902:e78f:b0:13d:f99f:34bb with SMTP id cp15-20020a170902e78f00b0013df99f34bbmr5220145plb.48.1633632318871; Thu, 07 Oct 2021 11:45:18 -0700 (PDT) Received: from srikanth-ThinkPad-T450.domain.name ([136.185.113.102]) by smtp.gmail.com with ESMTPSA id c11sm3311586pji.38.2021.10.07.11.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 11:45:18 -0700 (PDT) From: Srikanth Kaka To: Matan Azrad , Viacheslav Ovsiienko Cc: dev@dpdk.org, Vag Singh , Anand Thulasiram , Srikanth Kaka Date: Fri, 8 Oct 2021 00:13:33 +0530 Message-Id: <20211007184350.73858-25-srikanth.k@oneconvergence.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211007184350.73858-1-srikanth.k@oneconvergence.com> References: <20211007184350.73858-1-srikanth.k@oneconvergence.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 08 Oct 2021 12:55:54 +0200 Subject: [dpdk-dev] [PATCH v2 24/41] net/mlx5: read device clock X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" read device clock Signed-off-by: Srikanth Kaka Signed-off-by: Vag Singh Signed-off-by: Anand Thulasiram --- drivers/net/mlx5/freebsd/mlx5_ethdev_os.c | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/net/mlx5/freebsd/mlx5_ethdev_os.c b/drivers/net/mlx5/freebsd/mlx5_ethdev_os.c index d100addd51..5d66f17513 100644 --- a/drivers/net/mlx5/freebsd/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/freebsd/mlx5_ethdev_os.c @@ -11,6 +11,7 @@ #include +#include #include #include "mlx5.h" @@ -165,6 +166,36 @@ mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, unsigned int flags) return mlx5_ifreq(dev, SIOCSIFFLAGS, &request); } +/** + * Get device current raw clock counter + * + * @param dev + * Pointer to Ethernet device structure. + * @param[out] time + * Current raw clock counter of the device. + * + * @return + * 0 if the clock has correctly been read + * The value of errno in case of error + */ +int +mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct ibv_context *ctx = priv->sh->ctx; + struct ibv_values_ex values; + int err = 0; + + values.comp_mask = IBV_VALUES_MASK_RAW_CLOCK; + err = mlx5_glue->query_rt_values_ex(ctx, &values); + if (err != 0) { + DRV_LOG(WARNING, "Could not query the clock !"); + return err; + } + *clock = values.raw_clock.tv_nsec; + return 0; +} + static const struct ifmedia_baudrate ifmedia_baudrate_desc[] = IFM_BAUDRATE_DESCRIPTIONS;