From patchwork Thu Sep 23 09:58:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 99476 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6BC4A0C43; Thu, 23 Sep 2021 11:59:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9CE0841269; Thu, 23 Sep 2021 11:59:16 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 5EBBD41268 for ; Thu, 23 Sep 2021 11:59:13 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7F2F9113E; Thu, 23 Sep 2021 02:59:12 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EA4013F59C; Thu, 23 Sep 2021 02:59:10 -0700 (PDT) From: Feifei Wang To: Ruifeng Wang Cc: dev@dpdk.org, nd@arm.com, Feifei Wang Date: Thu, 23 Sep 2021 17:58:58 +0800 Message-Id: <20210923095902.301762-2-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210923095902.301762-1-feifei.wang2@arm.com> References: <20210902053253.3017858-1-feifei.wang2@arm.com> <20210923095902.301762-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [RFC PATCH v2 1/5] eal: add new definitions for wait scheme X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Introduce macros as generic interface for address monitoring. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/eal/arm/include/rte_pause_64.h | 151 ++++++++++++++++++---------- lib/eal/include/generic/rte_pause.h | 78 ++++++++++++++ 2 files changed, 175 insertions(+), 54 deletions(-) diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte_pause_64.h index e87d10b8cc..205510e044 100644 --- a/lib/eal/arm/include/rte_pause_64.h +++ b/lib/eal/arm/include/rte_pause_64.h @@ -31,20 +31,12 @@ static inline void rte_pause(void) /* Put processor into low power WFE(Wait For Event) state. */ #define __WFE() { asm volatile("wfe" : : : "memory"); } -static __rte_always_inline void -rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, - int memorder) -{ - uint16_t value; - - assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); - - /* - * Atomic exclusive load from addr, it returns the 16-bit content of - * *addr while making it 'monitored',when it is written by someone - * else, the 'monitored' state is cleared and a event is generated - * implicitly to exit WFE. - */ +/* + * Atomic exclusive load from addr, it returns the 16-bit content of + * *addr while making it 'monitored', when it is written by someone + * else, the 'monitored' state is cleared and a event is generated + * implicitly to exit WFE. + */ #define __LOAD_EXC_16(src, dst, memorder) { \ if (memorder == __ATOMIC_RELAXED) { \ asm volatile("ldxrh %w[tmp], [%x[addr]]" \ @@ -58,6 +50,52 @@ rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, : "memory"); \ } } +/* + * Atomic exclusive load from addr, it returns the 32-bit content of + * *addr while making it 'monitored', when it is written by someone + * else, the 'monitored' state is cleared and a event is generated + * implicitly to exit WFE. + */ +#define __LOAD_EXC_32(src, dst, memorder) { \ + if (memorder == __ATOMIC_RELAXED) { \ + asm volatile("ldxr %w[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } else { \ + asm volatile("ldaxr %w[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } } + +/* + * Atomic exclusive load from addr, it returns the 64-bit content of + * *addr while making it 'monitored', when it is written by someone + * else, the 'monitored' state is cleared and a event is generated + * implicitly to exit WFE. + */ +#define __LOAD_EXC_64(src, dst, memorder) { \ + if (memorder == __ATOMIC_RELAXED) { \ + asm volatile("ldxr %x[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } else { \ + asm volatile("ldaxr %x[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } } + +static __rte_always_inline void +rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, + int memorder) +{ + uint16_t value; + + assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); + __LOAD_EXC_16(addr, value, memorder) if (value != expected) { __SEVL() @@ -66,7 +104,6 @@ rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, __LOAD_EXC_16(addr, value, memorder) } while (value != expected); } -#undef __LOAD_EXC_16 } static __rte_always_inline void @@ -77,25 +114,6 @@ rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); - /* - * Atomic exclusive load from addr, it returns the 32-bit content of - * *addr while making it 'monitored',when it is written by someone - * else, the 'monitored' state is cleared and a event is generated - * implicitly to exit WFE. - */ -#define __LOAD_EXC_32(src, dst, memorder) { \ - if (memorder == __ATOMIC_RELAXED) { \ - asm volatile("ldxr %w[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } else { \ - asm volatile("ldaxr %w[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } } - __LOAD_EXC_32(addr, value, memorder) if (value != expected) { __SEVL() @@ -104,7 +122,6 @@ rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, __LOAD_EXC_32(addr, value, memorder) } while (value != expected); } -#undef __LOAD_EXC_32 } static __rte_always_inline void @@ -115,25 +132,6 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); - /* - * Atomic exclusive load from addr, it returns the 64-bit content of - * *addr while making it 'monitored',when it is written by someone - * else, the 'monitored' state is cleared and a event is generated - * implicitly to exit WFE. - */ -#define __LOAD_EXC_64(src, dst, memorder) { \ - if (memorder == __ATOMIC_RELAXED) { \ - asm volatile("ldxr %x[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } else { \ - asm volatile("ldaxr %x[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } } - __LOAD_EXC_64(addr, value, memorder) if (value != expected) { __SEVL() @@ -143,6 +141,51 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, } while (value != expected); } } + +#define rte_wait_event_16(addr, mask, expected, cond, memorder) \ +do { \ + uint16_t value \ + assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); \ + __LOAD_EXC_16(addr, value, memorder) \ + if ((value & mask) cond expected) { \ + __SEVL() \ + do { \ + __WFE() \ + __LOAD_EXC_16(addr, value, memorder) \ + } while ((value & mask) cond expected); \ + } \ +} while (0) + +#define rte_wait_event_32(addr, mask, expected, cond, memorder) \ +do { \ + uint32_t value \ + assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); \ + __LOAD_EXC_32(addr, value, memorder) \ + if ((value & mask) op expected) { \ + __SEVL() \ + do { \ + __WFE() \ + __LOAD_EXC_32(addr, value, memorder) \ + } while ((value & mask) cond expected); \ + } \ +} while (0) + +#define rte_wait_event_64(addr, mask, expected, cond, memorder) \ +do { \ + uint64_t value \ + assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); \ + __LOAD_EXC_64(addr, value, memorder) \ + if ((value & mask) cond expected) { \ + __SEVL() \ + do { \ + __WFE() \ + __LOAD_EXC_64(addr, value, memorder) \ + } while ((value & mask) cond expected); \ + } \ +} while (0) + +#undef __LOAD_EXC_16 +#undef __LOAD_EXC_32 #undef __LOAD_EXC_64 #undef __SEVL diff --git a/lib/eal/include/generic/rte_pause.h b/lib/eal/include/generic/rte_pause.h index 668ee4a184..4e32107eca 100644 --- a/lib/eal/include/generic/rte_pause.h +++ b/lib/eal/include/generic/rte_pause.h @@ -111,6 +111,84 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, while (__atomic_load_n(addr, memorder) != expected) rte_pause(); } + +/* + * Wait until a 16-bit *addr breaks the condition, with a relaxed memory + * ordering model meaning the loads around this API can be reordered. + * + * @param addr + * A pointer to the memory location. + * @param mask + * A mask of value bits in interest + * @param expected + * A 16-bit expected value to be in the memory location. + * @param cond + * A symbol representing the condition (==, !=). + * @param memorder + * Two different memory orders that can be specified: + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to + * C++11 memory orders with the same names, see the C++11 standard or + * the GCC wiki on atomic synchronization for detailed definition. + */ +#define rte_wait_event_16(addr, mask, expected, cond, memorder) \ +do { \ + assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); \ + \ + while ((__atomic_load_n(addr, memorder) & mask) cond expected) \ + rte_pause(); \ +} while (0) + +/* + * Wait until a 32-bit *addr breaks the condition, with a relaxed memory + * ordering model meaning the loads around this API can be reordered. + * + * @param addr + * A pointer to the memory location. + * @param mask + * A mask of value bits in interest. + * @param expected + * A 32-bit expected value to be in the memory location. + * @param cond + * A symbol representing the condition (==, !=). + * @param memorder + * Two different memory orders that can be specified: + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to + * C++11 memory orders with the same names, see the C++11 standard or + * the GCC wiki on atomic synchronization for detailed definition. + */ +#define rte_wait_event_32(addr, mask, expected, cond, memorder) \ +do { \ + assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); \ + \ + while ((__atomic_load_n(addr, memorder) & mask) cond expected) \ + rte_pause(); \ +} while (0) + +/* + * Wait until a 64-bit *addr breaks the condition, with a relaxed memory + * ordering model meaning the loads around this API can be reordered. + * + * @param addr + * A pointer to the memory location. + * @param mask + * A mask of value bits in interest + * @param expected + * A 64-bit expected value to be in the memory location. + * @param cond + * A symbol representing the condition (==, !=). + * @param memorder + * Two different memory orders that can be specified: + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to + * C++11 memory orders with the same names, see the C++11 standard or + * the GCC wiki on atomic synchronization for detailed definition. + */ +#define rte_wait_event_64(addr, mask, expected, cond, memorder) \ +do { \ + assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); \ + \ + while ((__atomic_load_n(addr, memorder) & mask) cond expected) \ + rte_pause(); \ +} while (0) #endif #endif /* _RTE_PAUSE_H_ */