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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT055.mail.protection.outlook.com (10.13.175.129) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:40:16 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:16 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:13 +0000 From: Tal Shnaiderman To: CC: , , , , , , , , Date: Tue, 14 Sep 2021 08:38:32 +0300 Message-ID: <20210914053833.7760-10-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: af23ec07-c4b8-45ee-3a30-08d9774221bb X-MS-TrafficTypeDiagnostic: DM6PR12MB2970: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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CAT:NONE; SFS:(4636009)(346002)(376002)(39860400002)(136003)(396003)(36840700001)(46966006)(2906002)(6666004)(82310400003)(4326008)(8676002)(7696005)(7636003)(336012)(426003)(54906003)(36860700001)(6286002)(316002)(47076005)(478600001)(70206006)(83380400001)(8936002)(2616005)(356005)(82740400003)(1076003)(86362001)(6916009)(5660300002)(186003)(36756003)(16526019)(26005)(55016002)(36906005)(70586007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:16.5391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af23ec07-c4b8-45ee-3a30-08d9774221bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2970 Subject: [dpdk-dev] [RFC PATCH 09/10] crypto/mlx5: fix size of UMR WQE X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The size of the UMR WQE allocated object is decided by a sizof operation on the struct, however since the struct contains a union of flexible array members this sizeof results can differ between compilers. GCC for example treats the union as 0 sized, MSVC adds a padding of 16Bits. To resolve the ambiguity the allocation size will be calculated by the sizes of the members excluding the flexible union. Fixes: a1978aa23bf4 ("crypto/mlx5: add maximum segments configuration") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman --- drivers/crypto/mlx5/mlx5_crypto.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 3f5a6745dc..4b8d561e33 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -1061,7 +1061,9 @@ mlx5_crypto_dev_probe(struct rte_device *dev) priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag); priv->max_segs_num = devarg_prms.max_segs_num; priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) + - sizeof(struct mlx5_umr_wqe) + + sizeof(struct mlx5_wqe_cseg) + + sizeof(struct mlx5_wqe_umr_cseg) + + sizeof(struct mlx5_wqe_mkey_cseg) + RTE_ALIGN(priv->max_segs_num, 4) * sizeof(struct mlx5_wqe_dseg); rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) +