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[RFC,09/10] crypto/mlx5: fix size of UMR WQE

Message ID 20210914053833.7760-10-talshn@nvidia.com (mailing list archive)
State Superseded
Delegated to: akhil goyal
Headers show
Series Support MLX5 crypto driver on Windows | expand


Context Check Description
ci/checkpatch success coding style OK

Commit Message

Tal Shnaiderman Sept. 14, 2021, 5:38 a.m. UTC
The size of the UMR WQE allocated object is decided by a sizof
operation on the struct, however since the struct contains
a union of flexible array members this sizeof results can differ
between compilers.

GCC for example treats the union as 0 sized, MSVC adds a padding
of 16Bits.

To resolve the ambiguity the allocation size will be calculated
by the sizes of the members excluding the flexible union.

Fixes: a1978aa23bf4 ("crypto/mlx5: add maximum segments configuration")
Cc: stable@dpdk.org

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
 drivers/crypto/mlx5/mlx5_crypto.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c
index 3f5a6745dc..4b8d561e33 100644
--- a/drivers/crypto/mlx5/mlx5_crypto.c
+++ b/drivers/crypto/mlx5/mlx5_crypto.c
@@ -1061,7 +1061,9 @@  mlx5_crypto_dev_probe(struct rte_device *dev)
 	priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag);
 	priv->max_segs_num = devarg_prms.max_segs_num;
 	priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) +
-			     sizeof(struct mlx5_umr_wqe) +
+			     sizeof(struct mlx5_wqe_cseg) +
+			     sizeof(struct mlx5_wqe_umr_cseg) +
+			     sizeof(struct mlx5_wqe_mkey_cseg) +
 			     RTE_ALIGN(priv->max_segs_num, 4) *
 			     sizeof(struct mlx5_wqe_dseg);
 	rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) +