[3/3] net/mlx5: Fix RSS RETA update
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Commit Message
This patch fixes RETA updating for entries above 64.
Without ithat, these entries are never updated as
calculated mask value will always be 0.
Fixes: 634efbc2c8c0 ("mlx5: support RETA query and update")
Cc: stable@dpdk.org
Cc: nelio.laranjeiro@6wind.com
Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---
drivers/net/mlx5/mlx5_rss.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
Hi, Maxime
Very nice catch, thank you for the patch.
Minor typo in the commit message "ithat" -> "that".
Besides this:
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Friday, September 10, 2021 12:18
> To: dev@dpdk.org; chenbo.xia@intel.com; amorenoz@redhat.com;
> david.marchand@redhat.com; andrew.rybchenko@oktetlabs.ru;
> ferruh.yigit@intel.com; Michael Baum <michaelba@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>
> Cc: stable@dpdk.org; NBU-Contact-N?lio Laranjeiro
> <nelio.laranjeiro@6wind.com>; Maxime Coquelin
> <maxime.coquelin@redhat.com>
> Subject: [PATCH 3/3] net/mlx5: Fix RSS RETA update
>
> This patch fixes RETA updating for entries above 64.
> Without ithat, these entries are never updated as calculated mask value will
> always be 0.
>
> Fixes: 634efbc2c8c0 ("mlx5: support RETA query and update")
> Cc: stable@dpdk.org
> Cc: nelio.laranjeiro@6wind.com
>
> Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>
> ---
> drivers/net/mlx5/mlx5_rss.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/mlx5/mlx5_rss.c b/drivers/net/mlx5/mlx5_rss.c index
> c32129cdc2..6dc52acee0 100644
> --- a/drivers/net/mlx5/mlx5_rss.c
> +++ b/drivers/net/mlx5/mlx5_rss.c
> @@ -211,7 +211,7 @@ mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
> for (idx = 0, i = 0; (i != reta_size); ++i) {
> idx = i / RTE_RETA_GROUP_SIZE;
> pos = i % RTE_RETA_GROUP_SIZE;
> - if (((reta_conf[idx].mask >> i) & 0x1) == 0)
> + if (((reta_conf[idx].mask >> pos) & 0x1) == 0)
> continue;
> MLX5_ASSERT(reta_conf[idx].reta[pos] < priv->rxqs_n);
> (*priv->reta_idx)[i] = reta_conf[idx].reta[pos];
> --
> 2.31.1
@@ -211,7 +211,7 @@ mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
for (idx = 0, i = 0; (i != reta_size); ++i) {
idx = i / RTE_RETA_GROUP_SIZE;
pos = i % RTE_RETA_GROUP_SIZE;
- if (((reta_conf[idx].mask >> i) & 0x1) == 0)
+ if (((reta_conf[idx].mask >> pos) & 0x1) == 0)
continue;
MLX5_ASSERT(reta_conf[idx].reta[pos] < priv->rxqs_n);
(*priv->reta_idx)[i] = reta_conf[idx].reta[pos];