diff mbox series

[v3,17/17] devbind: move idxd device ID to dmadev class

Message ID 20210908103016.1661914-18-kevin.laatz@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series add dmadev driver for idxd devices |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation warning apply issues

Commit Message

Kevin Laatz Sept. 8, 2021, 10:30 a.m. UTC 
  The dmadev library is the preferred abstraction for using IDXD devices and
will replace the rawdev implementation in future. This patch moves the IDXD
device ID to the dmadev class.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 usertools/dpdk-devbind.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Conor Walsh Sept. 9, 2021, 11:27 a.m. UTC | #1 
> The dmadev library is the preferred abstraction for using IDXD devices and
> will replace the rawdev implementation in future. This patch moves the IDXD
> device ID to the dmadev class.
>
> Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>

Reviewed-by: Conor Walsh <conor.walsh@intel.com>
diff mbox series

Patch

diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index 8bb573f4b0..98b698ccc0 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -69,13 +69,13 @@ 
 network_devices = [network_class, cavium_pkx, avp_vnic, ifpga_class]
 baseband_devices = [acceleration_class]
 crypto_devices = [encryption_class, intel_processor_class]
-dma_devices = []
+dma_devices = [intel_idxd_spr]
 eventdev_devices = [cavium_sso, cavium_tim, intel_dlb, octeontx2_sso]
 mempool_devices = [cavium_fpa, octeontx2_npa]
 compress_devices = [cavium_zip]
 regex_devices = [octeontx2_ree]
 misc_devices = [cnxk_bphy, cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx,
-                intel_ioat_icx, intel_idxd_spr, intel_ntb_skx, intel_ntb_icx,
+                intel_ioat_icx, intel_ntb_skx, intel_ntb_icx,
                 octeontx2_dma]
 
 # global dict ethernet devices present. Dictionary indexed by PCI address.