From patchwork Mon Sep 6 02:02:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Zhang X-Patchwork-Id: 98004 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B756A0C4D; Mon, 6 Sep 2021 04:16:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DAE39410FA; Mon, 6 Sep 2021 04:16:21 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id D547D410E9; Mon, 6 Sep 2021 04:16:19 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10098"; a="199391652" X-IronPort-AV: E=Sophos;i="5.85,271,1624345200"; d="scan'208";a="199391652" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2021 19:16:18 -0700 X-IronPort-AV: E=Sophos;i="5.85,271,1624345200"; d="scan'208";a="536351190" Received: from unknown (HELO intel-npg-odc-srv03.cd.intel.com) ([10.240.178.145]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2021 19:16:13 -0700 From: Robin Zhang To: dev@dpdk.org Cc: beilei.xing@intel.com, qi.z.zhang@intel.com, helin.zhang@intel.com, jingjing.wu@intel.com, remy.horton@intel.com, jijiang.liu@intel.com, jing.d.chen@intel.com, heqing.zhu@intel.com, cunming.liang@intel.com, wenzhuo.lu@intel.com, roy.fan.zhang@intel.com, andrey.chilikin@intel.com, echaudro@redhat.com, junfeng.guo@intel.com, stevex.yang@intel.com, Robin Zhang , stable@dpdk.org, Sylwester Dziedziuch Date: Mon, 6 Sep 2021 02:02:46 +0000 Message-Id: <20210906020258.1291688-7-robinx.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210906020258.1291688-1-robinx.zhang@intel.com> References: <20210618063851.3694702-1-robinx.zhang@intel.com> <20210906020258.1291688-1-robinx.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 06/18] net/i40e/base: fix PF reset failed X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" PF has to delete all the filters during reset. If it is fully loaded with filters then it is possible that it will take more than 200 ms to finish the reset resulting in timeout during pf_reset and PF reset failed, -15 error indication. Increasing the timeout value for PF reset from 200 to 1000 to give PF more time to finish reset if it is loaded with filters. Fixes: 1e32378f0774 ("i40e/base: increase PF reset max loop limit") Cc: stable@dpdk.org Signed-off-by: Sylwester Dziedziuch Signed-off-by: Robin Zhang --- drivers/net/i40e/base/i40e_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c index ceedec68bf..aa424e6010 100644 --- a/drivers/net/i40e/base/i40e_common.c +++ b/drivers/net/i40e/base/i40e_common.c @@ -1341,7 +1341,7 @@ STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw, return I40E_ERR_RESET_FAILED; } -#define I40E_PF_RESET_WAIT_COUNT 200 +#define I40E_PF_RESET_WAIT_COUNT 1000 /** * i40e_pf_reset - Reset the PF * @hw: pointer to the hardware structure