From patchwork Mon Jul 26 04:48:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kiran Kumar Kokkilagadda X-Patchwork-Id: 96271 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 42854A0C47; Mon, 26 Jul 2021 06:49:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8B5F7410F5; Mon, 26 Jul 2021 06:49:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D3784410EA for ; Mon, 26 Jul 2021 06:49:04 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16Q4k836020649 for ; Sun, 25 Jul 2021 21:49:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=2EPmNbX+ImfzFSlCon3PqbwXTO8GUEGiwLsJbJt/0+M=; b=RL7ctzwKEvzIRATsLnHxQ1Lo6DU1emfsJLWiq3t5DlaW83tz+Zx4zLps53HhTmLvcSwN RCbDX1cDE4m1EzsA6Y5yjl3oKmqBOHgm0UtMt20Xy6gaBbQUNypLX/xYuv3HJCaE66n8 aobudt5ZEVTEJjIuE2W/C271XOZQ2zUlifPtd6LsP+LbgsGPwjXLAuSjIQglPsJd0VrZ PmQJmLLHM4ICqP84SLbh47Z/9CG5PXzGj/M1Jft3qLu+y3FptzbMU2kDmPmCPt++meK/ IBU1ZF7h4c3c0ygpmnBdXt4pB3oWqxPrbE2w9Mlz9pQOHtYIptbvltQyCodrmNn+E/Ud Vg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3a1m9609sf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 25 Jul 2021 21:49:04 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 25 Jul 2021 21:49:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sun, 25 Jul 2021 21:49:02 -0700 Received: from localhost.localdomain (unknown [10.28.34.15]) by maili.marvell.com (Postfix) with ESMTP id 2B81B5E6868; Sun, 25 Jul 2021 21:48:58 -0700 (PDT) From: To: Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj CC: , Kiran Kumar K Date: Mon, 26 Jul 2021 10:18:52 +0530 Message-ID: <20210726044853.2232433-2-kirankumark@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210726044853.2232433-1-kirankumark@marvell.com> References: <20210726044853.2232433-1-kirankumark@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: oBvyTvn8BTnl918YDM7Ld4YfB_X6PCMm X-Proofpoint-GUID: oBvyTvn8BTnl918YDM7Ld4YfB_X6PCMm X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-26_01:2021-07-23, 2021-07-26 signatures=0 Subject: [dpdk-dev] [PATCH 2/3] crypto/cnxk: update asym ECDSA messages in sync with ucode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar K Adding changes to asymmetric ECDSA messages to align with the new ucode for cnxk device. Signed-off-by: Kiran Kumar K --- drivers/crypto/cnxk/cnxk_ae.h | 24 ++++++++++++++++++++---- drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h index c752e62ea5..174a940ab8 100644 --- a/drivers/crypto/cnxk/cnxk_ae.h +++ b/drivers/crypto/cnxk/cnxk_ae.h @@ -439,7 +439,7 @@ cnxk_ae_ecdsa_sign_prep(struct rte_crypto_ecdsa_op_param *ecdsa, * Please note, private key, order cannot exceed prime * length i.e 3 * p_align. */ - dlen = sizeof(fpm_table_iova) + k_align + m_align + p_align * 3; + dlen = sizeof(fpm_table_iova) + k_align + m_align + p_align * 5; memset(dptr, 0, dlen); @@ -461,12 +461,18 @@ cnxk_ae_ecdsa_sign_prep(struct rte_crypto_ecdsa_op_param *ecdsa, memcpy(dptr, ecdsa->message.data, message_len); dptr += m_align; + memcpy(dptr, ec_grp->consta.data, prime_len); + dptr += p_align; + + memcpy(dptr, ec_grp->constb.data, prime_len); + dptr += p_align; + /* Setup opcodes */ w4.s.opcode_major = ROC_AE_MAJOR_OP_ECDSA; w4.s.opcode_minor = ROC_AE_MINOR_OP_ECDSA_SIGN; w4.s.param1 = curveid | (message_len << 8); - w4.s.param2 = k_len; + w4.s.param2 = (pkey_len << 8) | k_len; w4.s.dlen = dlen; inst->w4.u64 = w4.u64; @@ -521,7 +527,7 @@ cnxk_ae_ecdsa_verify_prep(struct rte_crypto_ecdsa_op_param *ecdsa, * Please note sign, public key and order can not exceed prime length * i.e. 6 * p_align */ - dlen = sizeof(fpm_table_iova) + m_align + (6 * p_align); + dlen = sizeof(fpm_table_iova) + m_align + (8 * p_align); memset(dptr, 0, dlen); @@ -549,6 +555,12 @@ cnxk_ae_ecdsa_verify_prep(struct rte_crypto_ecdsa_op_param *ecdsa, memcpy(dptr + qy_offset, ecdsa->q.y.data, qy_len); dptr += p_align; + memcpy(dptr, ec_grp->consta.data, prime_len); + dptr += p_align; + + memcpy(dptr, ec_grp->constb.data, prime_len); + dptr += p_align; + /* Setup opcodes */ w4.s.opcode_major = ROC_AE_MAJOR_OP_ECDSA; w4.s.opcode_minor = ROC_AE_MINOR_OP_ECDSA_VERIFY; @@ -612,7 +624,7 @@ cnxk_ae_ecpm_prep(struct rte_crypto_ecpm_op_param *ecpm, * scalar length), * Please note point length is equivalent to prime of the curve */ - dlen = 3 * p_align + scalar_align; + dlen = 5 * p_align + scalar_align; x1_offset = prime_len - x1_len; y1_offset = prime_len - y1_len; @@ -628,6 +640,10 @@ cnxk_ae_ecpm_prep(struct rte_crypto_ecpm_op_param *ecpm, dptr += scalar_align; memcpy(dptr, ec_grp->prime.data, ec_grp->prime.length); dptr += p_align; + memcpy(dptr, ec_grp->consta.data, ec_grp->consta.length); + dptr += p_align; + memcpy(dptr, ec_grp->constb.data, ec_grp->constb.length); + dptr += p_align; /* Setup opcodes */ w4.s.opcode_major = ROC_AE_MAJOR_OP_ECC; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h index ff46d16e58..b3856f7eaa 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev.h @@ -13,7 +13,7 @@ #define CNXK_CPT_MAX_CAPS 34 #define CNXK_SEC_CRYPTO_MAX_CAPS 4 #define CNXK_SEC_MAX_CAPS 3 -#define CNXK_AE_EC_ID_MAX 5 +#define CNXK_AE_EC_ID_MAX 8 /** * Device private data */