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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT006.mail.protection.outlook.com (10.13.173.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4331.21 via Frontend Transport; Tue, 20 Jul 2021 13:10:10 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Jul 2021 13:10:08 +0000 From: Suanming Mou To: , CC: , , Date: Tue, 20 Jul 2021 16:09:32 +0300 Message-ID: <20210720130944.5407-4-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210720130944.5407-1-suanmingm@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210720130944.5407-1-suanmingm@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f2f4c149-e234-43d0-a516-08d94b7fb484 X-MS-TrafficTypeDiagnostic: BL0PR12MB2417: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; 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CAT:NONE; SFS:(4636009)(136003)(396003)(39860400002)(346002)(376002)(36840700001)(46966006)(36756003)(36906005)(47076005)(70206006)(83380400001)(356005)(426003)(86362001)(70586007)(54906003)(2616005)(110136005)(6286002)(82740400003)(316002)(6666004)(186003)(1076003)(16526019)(7636003)(2906002)(8676002)(82310400003)(4326008)(26005)(36860700001)(7696005)(5660300002)(55016002)(336012)(8936002)(478600001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2021 13:10:10.9598 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2f4c149-e234-43d0-a516-08d94b7fb484 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2417 Subject: [dpdk-dev] [PATCH v9 03/15] crypto/mlx5: add basic operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shiri Kuzin The basic dev control operations are configure, close, start, stop and get info. Extended the existing support of configure and close: -mlx5_crypto_dev_configure- function used to configure device. -mlx5_crypto_dev_close- function used to close a configured device. -mlx5_crypto_dev_stop- function used to stop device. -mlx5_crypto_dev_start- function used to start device. -mlx5_crypto_dev_infos_get- function used to get info. Added config struct to user private data with the fields socket id, number of queue pairs and feature flags to be disabled. Add the dev_start function that is used to start a configured device. Add the dev_stop function that is used to stop a configured device. Signed-off-by: Shiri Kuzin Acked-by: Matan Azrad --- drivers/crypto/mlx5/mlx5_crypto.c | 103 ++++++++++++++++++++++++++++-- drivers/crypto/mlx5/mlx5_crypto.h | 1 + 2 files changed, 99 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 34b4b52b04..9ad64f7244 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -30,6 +30,32 @@ int mlx5_crypto_logtype; uint8_t mlx5_crypto_driver_id; +const struct rte_cryptodev_capabilities mlx5_crypto_caps[] = { + { /* AES XTS */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_AES_XTS, + .block_size = 16, + .key_size = { + .min = 32, + .max = 64, + .increment = 32 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .dataunit_set = + RTE_CRYPTO_CIPHER_DATA_UNIT_LEN_512_BYTES | + RTE_CRYPTO_CIPHER_DATA_UNIT_LEN_4096_BYTES, + }, } + }, } + }, +}; + static const char mlx5_crypto_drv_name[] = RTE_STR(MLX5_CRYPTO_DRIVER_NAME); static const struct rte_driver mlx5_drv = { @@ -39,12 +65,79 @@ static const struct rte_driver mlx5_drv = { static struct cryptodev_driver mlx5_cryptodev_driver; +static void +mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev, + struct rte_cryptodev_info *dev_info) +{ + RTE_SET_USED(dev); + if (dev_info != NULL) { + dev_info->driver_id = mlx5_crypto_driver_id; + dev_info->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS; + dev_info->capabilities = mlx5_crypto_caps; + dev_info->max_nb_queue_pairs = 0; + dev_info->min_mbuf_headroom_req = 0; + dev_info->min_mbuf_tailroom_req = 0; + dev_info->sym.max_nb_sessions = 0; + /* + * If 0, the device does not have any limitation in number of + * sessions that can be used. + */ + } +} + +static int +mlx5_crypto_dev_configure(struct rte_cryptodev *dev, + struct rte_cryptodev_config *config) +{ + struct mlx5_crypto_priv *priv = dev->data->dev_private; + + if (config == NULL) { + DRV_LOG(ERR, "Invalid crypto dev configure parameters."); + return -EINVAL; + } + if ((config->ff_disable & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) != 0) { + DRV_LOG(ERR, + "Disabled symmetric crypto feature is not supported."); + return -ENOTSUP; + } + if (mlx5_crypto_dek_setup(priv) != 0) { + DRV_LOG(ERR, "Dek hash list creation has failed."); + return -ENOMEM; + } + priv->dev_config = *config; + DRV_LOG(DEBUG, "Device %u was configured.", dev->driver_id); + return 0; +} + +static void +mlx5_crypto_dev_stop(struct rte_cryptodev *dev) +{ + RTE_SET_USED(dev); +} + +static int +mlx5_crypto_dev_start(struct rte_cryptodev *dev) +{ + RTE_SET_USED(dev); + return 0; +} + +static int +mlx5_crypto_dev_close(struct rte_cryptodev *dev) +{ + struct mlx5_crypto_priv *priv = dev->data->dev_private; + + mlx5_crypto_dek_unset(priv); + DRV_LOG(DEBUG, "Device %u was closed.", dev->driver_id); + return 0; +} + static struct rte_cryptodev_ops mlx5_crypto_ops = { - .dev_configure = NULL, - .dev_start = NULL, - .dev_stop = NULL, - .dev_close = NULL, - .dev_infos_get = NULL, + .dev_configure = mlx5_crypto_dev_configure, + .dev_start = mlx5_crypto_dev_start, + .dev_stop = mlx5_crypto_dev_stop, + .dev_close = mlx5_crypto_dev_close, + .dev_infos_get = mlx5_crypto_dev_infos_get, .stats_get = NULL, .stats_reset = NULL, .queue_pair_setup = NULL, diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index 3f783fc956..11772bb846 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -24,6 +24,7 @@ struct mlx5_crypto_priv { uint32_t pdn; /* Protection Domain number. */ struct ibv_pd *pd; struct mlx5_hlist *dek_hlist; /* Dek hash list. */ + struct rte_cryptodev_config dev_config; }; struct mlx5_crypto_dek {