Add support for device init and fini. It merely saves
baseband phy state container in a globally accessible
resource chest.
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
drivers/common/cnxk/meson.build | 1 +
drivers/common/cnxk/roc_api.h | 4 +++
drivers/common/cnxk/roc_bphy.c | 40 +++++++++++++++++++++++++++++
drivers/common/cnxk/roc_bphy.h | 17 ++++++++++++
drivers/common/cnxk/roc_idev.c | 1 +
drivers/common/cnxk/roc_idev_priv.h | 2 ++
drivers/common/cnxk/version.map | 2 ++
7 files changed, 67 insertions(+)
create mode 100644 drivers/common/cnxk/roc_bphy.c
create mode 100644 drivers/common/cnxk/roc_bphy.h
@@ -11,6 +11,7 @@ endif
config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
deps = ['eal', 'pci', 'bus_pci', 'mbuf']
sources = files(
+ 'roc_bphy.c',
'roc_bphy_cgx.c',
'roc_dev.c',
'roc_idev.c',
@@ -50,6 +50,7 @@
#define PCI_DEVID_CNXK_EP_VF 0xB203
#define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6
#define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7
+#define PCI_DEVID_CNXK_BPHY 0xA089
#define PCI_DEVID_CN9K_CGX 0xA059
#define PCI_DEVID_CN10K_RPM 0xA060
@@ -103,4 +104,7 @@
/* Baseband phy cgx */
#include "roc_bphy_cgx.h"
+/* Baseband phy */
+#include "roc_bphy.h"
+
#endif /* _ROC_API_H_ */
new file mode 100644
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+int
+roc_bphy_dev_init(struct roc_bphy *roc_bphy)
+{
+ struct idev_cfg *idev;
+
+ idev = idev_get_cfg();
+ if (!idev)
+ return -ENODEV;
+
+ if (!roc_bphy || !roc_bphy->pci_dev)
+ return -EINVAL;
+
+ idev->bphy = roc_bphy;
+
+ return 0;
+}
+
+int
+roc_bphy_dev_fini(struct roc_bphy *roc_bphy)
+{
+ struct idev_cfg *idev;
+
+ idev = idev_get_cfg();
+ if (!idev)
+ return -ENODEV;
+
+ if (!roc_bphy)
+ return -EINVAL;
+
+ idev->bphy = NULL;
+
+ return 0;
+}
new file mode 100644
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2020 Marvell.
+ */
+
+#ifndef _ROC_BPHY_
+#define _ROC_BPHY_
+
+#include "roc_api.h"
+
+struct roc_bphy {
+ struct plt_pci_device *pci_dev;
+} __plt_cache_aligned;
+
+int __roc_api roc_bphy_dev_init(struct roc_bphy *roc_bphy);
+int __roc_api roc_bphy_dev_fini(struct roc_bphy *roc_bphy);
+
+#endif /* _ROC_BPHY_ */
@@ -36,6 +36,7 @@ idev_set_defaults(struct idev_cfg *idev)
idev->lmt_pf_func = 0;
idev->lmt_base_addr = 0;
idev->num_lmtlines = 0;
+ idev->bphy = NULL;
__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);
}
@@ -7,6 +7,7 @@
/* Intra device related functions */
struct npa_lf;
+struct roc_bphy;
struct idev_cfg {
uint16_t sso_pf_func;
uint16_t npa_pf_func;
@@ -16,6 +17,7 @@ struct idev_cfg {
uint16_t lmt_pf_func;
uint16_t num_lmtlines;
uint64_t lmt_base_addr;
+ struct roc_bphy *bphy;
};
/* Generic */
@@ -20,6 +20,8 @@ INTERNAL {
roc_bphy_cgx_set_link_state;
roc_bphy_cgx_start_rxtx;
roc_bphy_cgx_stop_rxtx;
+ roc_bphy_dev_fini;
+ roc_bphy_dev_init;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;