[2/2] eal: fix side effects in ptr align macros
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Commit Message
From: Pavan Nikhilesh <pbhagavatula@marvell.com>
Avoid expanding parameters inside RTE_*_ALIGN macros.
Update common_autotest to detect macro side effects.
Workaround static arrays relying on RTE_ALIGN macros.
Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: David Marchand <david.marchand@redhat.com>
---
app/test/test_common.c | 6 ++++++
drivers/net/e1000/e1000_ethdev.h | 7 ++++---
drivers/net/ixgbe/ixgbe_ethdev.h | 6 ++++--
drivers/net/txgbe/txgbe_ethdev.h | 6 ++++--
lib/eal/include/rte_common.h | 17 +++++++++++++----
lib/ethdev/rte_eth_ctrl.h | 5 +++--
6 files changed, 34 insertions(+), 13 deletions(-)
Comments
On Sun, 9 May 2021 22:48:02 +0530
<pbhagavatula@marvell.com> wrote:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>
> Avoid expanding parameters inside RTE_*_ALIGN macros.
> Update common_autotest to detect macro side effects.
> Workaround static arrays relying on RTE_ALIGN macros.
>
> Fixes: af75078fece3 ("first public release")
> Cc: stable@dpdk.org
>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> Signed-off-by: David Marchand <david.marchand@redhat.com>
Why not split these up? It looks like the Intel driver and common part
could be separate?
>On Sun, 9 May 2021 22:48:02 +0530
><pbhagavatula@marvell.com> wrote:
>
>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>
>> Avoid expanding parameters inside RTE_*_ALIGN macros.
>> Update common_autotest to detect macro side effects.
>> Workaround static arrays relying on RTE_ALIGN macros.
>>
>> Fixes: af75078fece3 ("first public release")
>> Cc: stable@dpdk.org
>>
>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>> Signed-off-by: David Marchand <david.marchand@redhat.com>
>
>Why not split these up? It looks like the Intel driver and common part
>could be separate?
The common changes break intel/mlx5 driver compilation can't separate them.
Hello Pavan,
On Mon, May 10, 2021 at 11:50 AM Pavan Nikhilesh Bhagavatula
<pbhagavatula@marvell.com> wrote:
>
> >On Sun, 9 May 2021 22:48:02 +0530
> ><pbhagavatula@marvell.com> wrote:
> >
> >> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> >>
> >> Avoid expanding parameters inside RTE_*_ALIGN macros.
> >> Update common_autotest to detect macro side effects.
> >> Workaround static arrays relying on RTE_ALIGN macros.
> >>
> >> Fixes: af75078fece3 ("first public release")
> >> Cc: stable@dpdk.org
> >>
> >> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> >> Signed-off-by: David Marchand <david.marchand@redhat.com>
> >
> >Why not split these up? It looks like the Intel driver and common part
> >could be separate?
>
> The common changes break intel/mlx5 driver compilation can't separate them.
Thanks for working on this.
The CI still reports a build error in mlx5.
@@ -69,6 +69,12 @@ test_macros(int __rte_unused unused_parm)
TEST_SIDE_EFFECT_2(RTE_PTR_ADD, void *, size_t);
TEST_SIDE_EFFECT_2(RTE_PTR_DIFF, void *, void *);
TEST_SIDE_EFFECT_2(RTE_PTR_SUB, void *, size_t);
+ TEST_SIDE_EFFECT_2(RTE_PTR_ALIGN, void *, size_t);
+ TEST_SIDE_EFFECT_2(RTE_PTR_ALIGN_CEIL, void *, size_t);
+ TEST_SIDE_EFFECT_2(RTE_PTR_ALIGN_FLOOR, void *, size_t);
+ TEST_SIDE_EFFECT_2(RTE_ALIGN, unsigned int, unsigned int);
+ TEST_SIDE_EFFECT_2(RTE_ALIGN_CEIL, unsigned int, unsigned int);
+ TEST_SIDE_EFFECT_2(RTE_ALIGN_FLOOR, unsigned int, unsigned int);
TEST_SIDE_EFFECT_2(RTE_ALIGN_MUL_CEIL, unsigned int, unsigned int);
TEST_SIDE_EFFECT_2(RTE_ALIGN_MUL_FLOOR, unsigned int, unsigned int);
TEST_SIDE_EFFECT_2(RTE_ALIGN_MUL_NEAR, unsigned int, unsigned int);
@@ -332,9 +332,10 @@ struct igb_eth_syn_filter_ele {
};
#define IGB_FLEX_FILTER_MAXLEN 128 /**< bytes to use in flex filter. */
-#define IGB_FLEX_FILTER_MASK_SIZE \
- (RTE_ALIGN(IGB_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
- /**< mask bytes in flex filter. */
+#define IGB_FLEX_FILTER_MASK_SIZE \
+ (RTE_ALIGN_FLOOR(IGB_FLEX_FILTER_MAXLEN + (CHAR_BIT - 1), CHAR_BIT) / \
+ CHAR_BIT)
+/**< mask bytes in flex filter. */
/**
* A structure used to define the flex filter entry
@@ -311,8 +311,10 @@ struct ixgbe_5tuple_filter {
uint16_t queue; /* rx queue assigned to */
};
-#define IXGBE_5TUPLE_ARRAY_SIZE \
- (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
+#define IXGBE_5TUPLE_ARRAY_SIZE \
+ (RTE_ALIGN_FLOOR(IXGBE_MAX_FTQF_FILTERS + (sizeof(uint32_t) * NBBY) - \
+ 1, \
+ (sizeof(uint32_t) * NBBY)) / \
(sizeof(uint32_t) * NBBY))
struct ixgbe_ethertype_filter {
@@ -219,8 +219,10 @@ struct txgbe_5tuple_filter {
uint16_t queue; /* rx queue assigned to */
};
-#define TXGBE_5TUPLE_ARRAY_SIZE \
- (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
+#define TXGBE_5TUPLE_ARRAY_SIZE \
+ (RTE_ALIGN_FLOOR(TXGBE_MAX_FTQF_FILTERS + (sizeof(uint32_t) * NBBY) - \
+ 1, \
+ (sizeof(uint32_t) * NBBY)) / \
(sizeof(uint32_t) * NBBY))
struct txgbe_ethertype_filter {
@@ -294,8 +294,13 @@ static void __attribute__((destructor(RTE_PRIO(prio)), used)) func(void)
* point to an address no lower than the first parameter. Second parameter
* must be a power-of-two value.
*/
-#define RTE_PTR_ALIGN_CEIL(ptr, align) \
- RTE_PTR_ALIGN_FLOOR((typeof(ptr))RTE_PTR_ADD(ptr, (align) - 1), align)
+#define RTE_PTR_ALIGN_CEIL(ptr, align) \
+ __extension__({ \
+ typeof(ptr) _pc = (ptr); \
+ typeof(align) _ac = (align); \
+ RTE_PTR_ALIGN_FLOOR((typeof(ptr))RTE_PTR_ADD(_pc, _ac - 1), \
+ _ac); \
+ })
/**
* Macro to align a value to a given power-of-two. The resultant value
@@ -303,8 +308,12 @@ static void __attribute__((destructor(RTE_PRIO(prio)), used)) func(void)
* than the first parameter. Second parameter must be a power-of-two
* value.
*/
-#define RTE_ALIGN_CEIL(val, align) \
- RTE_ALIGN_FLOOR(((val) + ((typeof(val)) (align) - 1)), align)
+#define RTE_ALIGN_CEIL(val, align) \
+ __extension__({ \
+ typeof(val) _vc = (val); \
+ typeof(val) _ac = (typeof(val))(align); \
+ RTE_ALIGN_FLOOR((_vc + _ac - 1), _ac); \
+ })
/**
* Macro to align a pointer to a given power-of-two. The resultant
@@ -431,8 +431,9 @@ enum rte_fdir_mode {
};
#define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
-#define RTE_FLOW_MASK_ARRAY_SIZE \
- (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
+#define RTE_FLOW_MASK_ARRAY_SIZE \
+ (RTE_ALIGN_FLOOR(RTE_ETH_FLOW_MAX + (UINT64_BIT - 1), UINT64_BIT) / \
+ UINT64_BIT)
/**
* A structure used to get the information of flow director filter.