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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT043.mail.protection.outlook.com (10.13.177.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4108.25 via Frontend Transport; Wed, 5 May 2021 09:50:59 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 5 May 2021 09:50:56 +0000 From: Bing Zhao To: , , CC: , , Date: Wed, 5 May 2021 12:50:08 +0300 Message-ID: <20210505095009.40250-17-bingz@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210505095009.40250-1-bingz@nvidia.com> References: <20210427153811.11554-1-bingz@nvidia.com> <20210505095009.40250-1-bingz@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3f974245-0996-4775-78ea-08d90fab496e X-MS-TrafficTypeDiagnostic: BN9PR12MB5196: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:352; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2021 09:50:59.2768 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f974245-0996-4775-78ea-08d90fab496e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5196 Subject: [dpdk-dev] [PATCH v6 16/17] net/mlx5: add support of CT between two ports X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" After creating a connection tracking context, it can be used between two ports. For each port, the flow for one direction traffic will be created. The context can only be shared between the owner port and the peer port that was specified when being created. Only the owner port could update the context or query it in current implementation. Signed-off-by: Bing Zhao --- drivers/net/mlx5/mlx5_flow.h | 57 +++++++++++++++++++++++++- drivers/net/mlx5/mlx5_flow_dv.c | 71 +++++++++++++++++++++++++-------- 2 files changed, 110 insertions(+), 18 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index e6b9d1def0..04c8806bf6 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -49,6 +49,25 @@ enum { MLX5_INDIRECT_ACTION_TYPE_CT, }; +/* Now, the maximal ports will be supported is 256, action number is 4M. */ +#define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100 + +#define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22 +#define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1) + +/* 30-31: type, 22-29: owner port, 0-21: index. */ +#define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \ + ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \ + (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \ + MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index)) + +#define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \ + (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \ + MLX5_INDIRECT_ACT_CT_OWNER_MASK) + +#define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \ + ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1)) + /* Matches on selected register. */ struct mlx5_rte_flow_item_tag { enum modify_reg id; @@ -1334,7 +1353,7 @@ mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item) } /* - * Get ASO CT action by index. + * Get ASO CT action by device and index. * * @param[in] dev * Pointer to the Ethernet device structure. @@ -1345,7 +1364,7 @@ mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item) * The specified ASO CT action pointer. */ static inline struct mlx5_aso_ct_action * -flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t idx) +flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx) { struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng; @@ -1360,6 +1379,40 @@ flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t idx) return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL]; } +/* + * Get ASO CT action by owner & index. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * @param[in] idx + * Index to the ASO CT action and owner port combination. + * + * @return + * The specified ASO CT action pointer. + */ +static inline struct mlx5_aso_ct_action * +flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_aso_ct_action *ct; + uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx); + uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx); + + if (owner == PORT_ID(priv)) { + ct = flow_aso_ct_get_by_dev_idx(dev, idx); + } else { + struct rte_eth_dev *owndev = &rte_eth_devices[owner]; + + MLX5_ASSERT(owner < RTE_MAX_ETHPORTS); + if (dev->data->dev_started != 1) + return NULL; + ct = flow_aso_ct_get_by_dev_idx(owndev, idx); + if (ct->peer != PORT_ID(priv)) + return NULL; + } + return ct; +} + int mlx5_flow_group_to_table(struct rte_eth_dev *dev, const struct mlx5_flow_tunnel *tunnel, uint32_t group, uint32_t *table, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index b691781fee..076a2493c1 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -11684,7 +11684,7 @@ flow_dv_prepare_counter(struct rte_eth_dev *dev, } /* - * Release an ASO CT action. + * Release an ASO CT action by its own device. * * @param[in] dev * Pointer to the Ethernet device structure. @@ -11695,12 +11695,12 @@ flow_dv_prepare_counter(struct rte_eth_dev *dev, * 0 when CT action was removed, otherwise the number of references. */ static inline int -flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t idx) +flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx) { struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng; uint32_t ret; - struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_idx(dev, idx); + struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx); enum mlx5_aso_ct_state state = __atomic_load_n(&ct->state, __ATOMIC_RELAXED); @@ -11729,7 +11729,21 @@ flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t idx) LIST_INSERT_HEAD(&mng->free_cts, ct, next); rte_spinlock_unlock(&mng->ct_sl); } - return ret; + return (int)ret; +} + +static inline int +flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx) +{ + uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx); + uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx); + struct rte_eth_dev *owndev = &rte_eth_devices[owner]; + RTE_SET_USED(dev); + + MLX5_ASSERT(owner < RTE_MAX_ETHPORTS); + if (dev->data->dev_started != 1) + return -1; + return flow_dv_aso_ct_dev_release(owndev, idx); } /* @@ -11881,7 +11895,7 @@ flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error) RTE_SET_USED(reg_c); #endif if (!ct->dr_action_orig) { - flow_dv_aso_ct_release(dev, ct_idx); + flow_dv_aso_ct_dev_release(dev, ct_idx); rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "failed to create ASO CT action"); @@ -11897,7 +11911,7 @@ flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error) reg_c - REG_C_0); #endif if (!ct->dr_action_rply) { - flow_dv_aso_ct_release(dev, ct_idx); + flow_dv_aso_ct_dev_release(dev, ct_idx); rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "failed to create ASO CT action"); @@ -11939,12 +11953,13 @@ flow_dv_translate_create_conntrack(struct rte_eth_dev *dev, return rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "Failed to allocate CT object"); - ct = flow_aso_ct_get_by_idx(dev, idx); + ct = flow_aso_ct_get_by_dev_idx(dev, idx); if (mlx5_aso_ct_update_by_wqe(sh, ct, pro)) return rte_flow_error_set(error, EBUSY, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "Failed to update CT"); ct->is_original = !!pro->is_original_dir; + ct->peer = pro->peer_port; return idx; } @@ -12110,7 +12125,7 @@ flow_dv_translate(struct rte_eth_dev *dev, int action_type = actions->type; const struct rte_flow_action *found_action = NULL; uint32_t jump_group = 0; - uint32_t ct_idx; + uint32_t owner_idx; struct mlx5_aso_ct_action *ct; if (!mlx5_flow_os_action_supported(action_type)) @@ -12566,8 +12581,13 @@ flow_dv_translate(struct rte_eth_dev *dev, action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD; break; case RTE_FLOW_ACTION_TYPE_CONNTRACK: - ct_idx = (uint32_t)(uintptr_t)action->conf; - ct = flow_aso_ct_get_by_idx(dev, ct_idx); + owner_idx = (uint32_t)(uintptr_t)action->conf; + ct = flow_aso_ct_get_by_idx(dev, owner_idx); + if (!ct) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, + "Failed to get CT object."); if (mlx5_aso_ct_available(priv->sh, ct)) return rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION, @@ -12580,7 +12600,7 @@ flow_dv_translate(struct rte_eth_dev *dev, dev_flow->dv.actions[actions_n] = ct->dr_action_rply; flow->indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT; - flow->ct = ct_idx; + flow->ct = owner_idx; __atomic_fetch_add(&ct->refcnt, 1, __ATOMIC_RELAXED); actions_n++; action_flags |= MLX5_FLOW_ACTION_CT; @@ -14220,8 +14240,7 @@ flow_dv_action_create(struct rte_eth_dev *dev, case RTE_FLOW_ACTION_TYPE_CONNTRACK: ret = flow_dv_translate_create_conntrack(dev, action->conf, err); - idx = (MLX5_INDIRECT_ACTION_TYPE_CT << - MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret; + idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret); break; default: rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, @@ -14287,7 +14306,9 @@ flow_dv_action_destroy(struct rte_eth_dev *dev, return 0; case MLX5_INDIRECT_ACTION_TYPE_CT: ret = flow_dv_aso_ct_release(dev, idx); - if (ret) + if (ret < 0) + return ret; + if (ret > 0) DRV_LOG(DEBUG, "Connection tracking object %u still " "has references %d.", idx, ret); return 0; @@ -14391,8 +14412,16 @@ __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx, struct mlx5_aso_ct_action *ct; const struct rte_flow_action_conntrack *new_prf; int ret = 0; + uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx); + uint32_t dev_idx; - ct = flow_aso_ct_get_by_idx(dev, idx); + if (PORT_ID(priv) != owner) + return rte_flow_error_set(error, EACCES, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "CT object owned by another port"); + dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx); + ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx); if (!ct->refcnt) return rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, @@ -15083,6 +15112,8 @@ flow_dv_action_query(struct rte_eth_dev *dev, uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_aso_ct_action *ct; + uint16_t owner; + uint32_t dev_idx; switch (type) { case MLX5_INDIRECT_ACTION_TYPE_AGE: @@ -15099,7 +15130,15 @@ flow_dv_action_query(struct rte_eth_dev *dev, case MLX5_INDIRECT_ACTION_TYPE_COUNT: return flow_dv_query_count(dev, idx, data, error); case MLX5_INDIRECT_ACTION_TYPE_CT: - ct = flow_aso_ct_get_by_idx(dev, idx); + owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx); + if (owner != PORT_ID(priv)) + return rte_flow_error_set(error, EACCES, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "CT object owned by another port"); + dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx); + ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx); + MLX5_ASSERT(ct); if (!ct->refcnt) return rte_flow_error_set(error, EFAULT, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,