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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT067.mail.protection.outlook.com (10.13.177.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4108.25 via Frontend Transport; Wed, 5 May 2021 08:06:24 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 5 May 2021 08:06:22 +0000 From: Bing Zhao To: , , CC: , , Date: Wed, 5 May 2021 11:05:45 +0300 Message-ID: <20210505080600.33749-3-bingz@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210505080600.33749-1-bingz@nvidia.com> References: <20210427153811.11554-1-bingz@nvidia.com> <20210505080600.33749-1-bingz@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6f4748df-5045-463c-6ff0-08d90f9cad93 X-MS-TrafficTypeDiagnostic: BL0PR12MB2420: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2021 08:06:24.9482 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f4748df-5045-463c-6ff0-08d90f9cad93 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2420 Subject: [dpdk-dev] [PATCH v5 02/17] common/mlx5: add CT offload capability checking X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" During startup, the ASO connection tracking offload capability could be queried via HCA_CAP_QUERY command. If the HW doesn't support ASO CT, the value would be 0 by default. The following initialization should be skipped and the creation of the CT object should return a failure directly. The following CT creation should also check this capability. With the old driver, the pre-processing macro should be used in order to make the compiling pass. Signed-off-by: Bing Zhao --- drivers/common/mlx5/linux/meson.build | 2 ++ drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++ drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h | 3 +++ 4 files changed, 9 insertions(+) diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index 3334bd5cb2..007834a49b 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -189,6 +189,8 @@ has_sym_args = [ 'MLX5_WQE_UMR_CTRL_FLAG_INLINE' ], [ 'HAVE_MLX5_DR_FLOW_DUMP_RULE', 'infiniband/mlx5dv.h', 'mlx5dv_dump_dr_rule' ], + [ 'HAVE_MLX5_DR_ACTION_ASO_CT', 'infiniband/mlx5dv.h', + 'MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR' ], ] config = configuration_data() foreach arg:has_sym_args diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 79fff6457c..ad67883fde 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -760,6 +760,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); attr->umr_modify_entity_size_disabled = MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); + attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, + general_obj_types) & + MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); if (attr->qos.sup) { MLX5_SET(query_hca_cap_in, in, op_mod, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 870bdb6b30..746320cf04 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -137,6 +137,7 @@ struct mlx5_hca_attr { uint32_t qp_ts_format:2; uint32_t regex:1; uint32_t reg_c_preserve:1; + uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; uint32_t geneve_tlv_opt; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 4da89d3379..71bdf43668 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1134,6 +1134,8 @@ enum { (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ (1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT) +#define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD) enum { MLX5_HCA_CAP_OPMOD_GET_MAX = 0, @@ -2456,6 +2458,7 @@ enum { MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, + MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031, }; struct mlx5_ifc_general_obj_in_cmd_hdr_bits {