From patchwork Tue May 4 00:27:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92713 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56084A0562; Tue, 4 May 2021 02:31:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D6C9641145; Tue, 4 May 2021 02:29:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id EBF76411AD for ; Tue, 4 May 2021 02:29:41 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AGOS002337 for ; Mon, 3 May 2021 17:29:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=661q1jEiZ9bRBapYxo/qzhse9SfGNSn9QprRrofjJUM=; b=edvJQnR0MINGVa3xFIHQD5xKAv6grWhm7/OQiGlrpJVFcLHehZAJn9E3XlzCDcortG/h vCNk0ZBjrKZ8ISszBx7AZT1u8T22g+K8cpD4tUqAqIXd8DWoNmM8JxvJPKj+9NtIV+e+ KCnSi7f4BtpD2FQyD7eHpt3nDCNnwzdj1+qGa5iX7Jmcn/5ybyT2B05Uv/s+NuE6R6YY KPqnt0/KciF7GG3v5LhsZ9hixCilB9ocWV+zDlKApxchpmY6YXhaCCcuBRomqPSBeuMe V3iHakwcedf7yp1i2v6K9yUdp3RP08bee8sLupTqHA9Anfeo80tWAbz+T3LNsxR9w6JH LQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6qg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:41 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:39 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:38 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id D7FE13F703F; Mon, 3 May 2021 17:29:37 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:25 +0530 Message-ID: <20210504002726.525-36-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Rw63jrtV1GMljexHHM9d_D1XAeEKOc1q X-Proofpoint-ORIG-GUID: Rw63jrtV1GMljexHHM9d_D1XAeEKOc1q X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 35/35] event/cnxk: add devargs to control timer adapters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add devargs to control each event timer adapter i.e. TIM rings internal parameters uniquely. The following dict format is expected [ring-chnk_slots-disable_npa-stats_ena]. 0 represents default values. Example: --dev "0002:1e:00.0,tim_ring_ctl=[2-1023-1-0]" Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 11 ++++ drivers/event/cnxk/cnxk_tim_evdev.c | 96 ++++++++++++++++++++++++++++- drivers/event/cnxk/cnxk_tim_evdev.h | 10 +++ 3 files changed, 116 insertions(+), 1 deletion(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index 11145dd7d..1bd935abc 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -135,6 +135,17 @@ Runtime Config Options -a 0002:0e:00.0,tim_rings_lmt=5 +- ``TIM ring control internal parameters`` + + When using multiple TIM rings the ``tim_ring_ctl`` devargs can be used to + control each TIM rings internal parameters uniquely. The following dict + format is expected [ring-chnk_slots-disable_npa-stats_ena]. 0 represents + default values. + + For Example:: + + -a 0002:0e:00.0,tim_ring_ctl=[2-1023-1-0] + Debugging Options ----------------- diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 19b71b4f5..9d40e336d 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -121,7 +121,7 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf; struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); struct cnxk_tim_ring *tim_ring; - int rc; + int i, rc; if (dev == NULL) return -ENODEV; @@ -165,6 +165,20 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->disable_npa = dev->disable_npa; tim_ring->enable_stats = dev->enable_stats; + for (i = 0; i < dev->ring_ctl_cnt; i++) { + struct cnxk_tim_ctl *ring_ctl = &dev->ring_ctl_data[i]; + + if (ring_ctl->ring == tim_ring->ring_id) { + tim_ring->chunk_sz = + ring_ctl->chunk_slots ? + ((uint32_t)(ring_ctl->chunk_slots + 1) * + CNXK_TIM_CHUNK_ALIGNMENT) : + tim_ring->chunk_sz; + tim_ring->enable_stats = ring_ctl->enable_stats; + tim_ring->disable_npa = ring_ctl->disable_npa; + } + } + if (tim_ring->disable_npa) { tim_ring->nb_chunks = tim_ring->nb_timers / @@ -368,6 +382,84 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, return 0; } +static void +cnxk_tim_parse_ring_param(char *value, void *opaque) +{ + struct cnxk_tim_evdev *dev = opaque; + struct cnxk_tim_ctl ring_ctl = {0}; + char *tok = strtok(value, "-"); + struct cnxk_tim_ctl *old_ptr; + uint16_t *val; + + val = (uint16_t *)&ring_ctl; + + if (!strlen(value)) + return; + + while (tok != NULL) { + *val = atoi(tok); + tok = strtok(NULL, "-"); + val++; + } + + if (val != (&ring_ctl.enable_stats + 1)) { + plt_err("Invalid ring param expected [ring-chunk_sz-disable_npa-enable_stats]"); + return; + } + + dev->ring_ctl_cnt++; + old_ptr = dev->ring_ctl_data; + dev->ring_ctl_data = + rte_realloc(dev->ring_ctl_data, + sizeof(struct cnxk_tim_ctl) * dev->ring_ctl_cnt, 0); + if (dev->ring_ctl_data == NULL) { + dev->ring_ctl_data = old_ptr; + dev->ring_ctl_cnt--; + return; + } + + dev->ring_ctl_data[dev->ring_ctl_cnt - 1] = ring_ctl; +} + +static void +cnxk_tim_parse_ring_ctl_list(const char *value, void *opaque) +{ + char *s = strdup(value); + char *start = NULL; + char *end = NULL; + char *f = s; + + while (*s) { + if (*s == '[') + start = s; + else if (*s == ']') + end = s; + + if (start && start < end) { + *end = 0; + cnxk_tim_parse_ring_param(start + 1, opaque); + start = end; + s = end; + } + s++; + } + + free(f); +} + +static int +cnxk_tim_parse_kvargs_dict(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + /* Dict format [ring-chunk_sz-disable_npa-enable_stats] use '-' as ',' + * isn't allowed. 0 represents default. + */ + cnxk_tim_parse_ring_ctl_list(value, opaque); + + return 0; +} + static void cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev) { @@ -388,6 +480,8 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev) &dev->enable_stats); rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value, &dev->min_ring_cnt); + rte_kvargs_process(kvlist, CNXK_TIM_RING_CTL, + &cnxk_tim_parse_kvargs_dict, &dev); rte_kvargs_free(kvlist); } diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index b5e4cfc9e..c369f6f47 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -38,6 +38,7 @@ #define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots" #define CNXK_TIM_STATS_ENA "tim_stats_ena" #define CNXK_TIM_RINGS_LMT "tim_rings_lmt" +#define CNXK_TIM_RING_CTL "tim_ring_ctl" #define CNXK_TIM_SP 0x1 #define CNXK_TIM_MP 0x2 @@ -75,6 +76,13 @@ #define TIM_BUCKET_SEMA_WLOCK \ (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK)) +struct cnxk_tim_ctl { + uint16_t ring; + uint16_t chunk_slots; + uint16_t disable_npa; + uint16_t enable_stats; +}; + struct cnxk_tim_evdev { struct roc_tim tim; struct rte_eventdev *event_dev; @@ -85,6 +93,8 @@ struct cnxk_tim_evdev { uint16_t chunk_slots; uint16_t min_ring_cnt; uint8_t enable_stats; + uint16_t ring_ctl_cnt; + struct cnxk_tim_ctl *ring_ctl_data; }; enum cnxk_tim_clk_src {