From patchwork Tue May 4 00:27:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92691 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F75CA0562; Tue, 4 May 2021 02:29:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE1B041175; Tue, 4 May 2021 02:28:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7343041168 for ; Tue, 4 May 2021 02:28:38 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440P25T025320 for ; Mon, 3 May 2021 17:28:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=jU/2bj/lg040KVdWj4Wunhh3j4axtFy1iNF4f+iBrw0=; b=f3o8Yir0Z7NfKR/9VCpbvPsxZ9KD+eQ/5QxA5kaGZOWEUesqUV2sbT8JBIj2rz1snvrb KX+PoRDhldOPEB2i8dO4LTmgiuRJkbdVpPyR0Ry4kOfj/oOpSClhIP+BKGLnVN5dkEik xKyNScBwWm9e+OIHfikwjIegdzlIym76rfQVY5Z+Ro9CG/8GJSdFSFfK1/PkbPN93sB/ PhhzhDTMoOO/Ok8Kcht8ElylFtdoq1ZkVnIFfm3u3gOHB7BWdqMnuaKCcmZPxth03+MY /PxEGA/WG90pbN3gM2t9cNGQqYM4FoamWubRG0v5tO7TxnuDdNtjUIPOc9kXXCxkP4Oo 6A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnpe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:36 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 9A89E3F703F; Mon, 3 May 2021 17:28:34 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:03 +0530 Message-ID: <20210504002726.525-14-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ohHWN9kOcuPG4rYHKG0LWE5hQYl8RfA4 X-Proofpoint-ORIG-GUID: ohHWN9kOcuPG4rYHKG0LWE5hQYl8RfA4 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 13/35] event/cnxk: add event port link and unlink X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add platform specific event port, queue link and unlink APIs. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 64 +++++++++++++++++- drivers/event/cnxk/cn9k_eventdev.c | 101 ++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.c | 36 ++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 12 +++- 4 files changed, 210 insertions(+), 3 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index fcdc1cf84..db8fe8169 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -63,6 +63,24 @@ cn10k_sso_init_hws_mem(void *arg, uint8_t port_id) return ws; } +static int +cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn10k_sso_hws *ws = port; + + return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link); +} + +static int +cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn10k_sso_hws *ws = port; + + return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link); +} + static void cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) { @@ -83,9 +101,12 @@ cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) static void cn10k_sso_hws_release(void *arg, void *hws) { + struct cnxk_sso_evdev *dev = arg; struct cn10k_sso_hws *ws = hws; + int i; - RTE_SET_USED(arg); + for (i = 0; i < dev->nb_event_queues; i++) + roc_sso_hws_unlink(&dev->sso, ws->hws_id, (uint16_t *)&i, 1); memset(ws, 0, sizeof(*ws)); } @@ -149,6 +170,12 @@ cn10k_sso_dev_configure(const struct rte_eventdev *event_dev) if (rc < 0) goto cnxk_rsrc_fini; + /* Restore any prior port-queue mapping. */ + cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link); + + dev->configured = 1; + rte_mb(); + return 0; cnxk_rsrc_fini: roc_sso_rsrc_fini(&dev->sso); @@ -184,6 +211,38 @@ cn10k_sso_port_release(void *port) rte_free(gws_cookie); } +static int +cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port, + const uint8_t queues[], const uint8_t priorities[], + uint16_t nb_links) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t hwgrp_ids[nb_links]; + uint16_t link; + + RTE_SET_USED(priorities); + for (link = 0; link < nb_links; link++) + hwgrp_ids[link] = queues[link]; + nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links); + + return (int)nb_links; +} + +static int +cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, + uint8_t queues[], uint16_t nb_unlinks) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t hwgrp_ids[nb_unlinks]; + uint16_t unlink; + + for (unlink = 0; unlink < nb_unlinks; unlink++) + hwgrp_ids[unlink] = queues[unlink]; + nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks); + + return (int)nb_unlinks; +} + static struct rte_eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, .dev_configure = cn10k_sso_dev_configure, @@ -193,6 +252,9 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .port_def_conf = cnxk_sso_port_def_conf, .port_setup = cn10k_sso_port_setup, .port_release = cn10k_sso_port_release, + .port_link = cn10k_sso_port_link, + .port_unlink = cn10k_sso_port_unlink, + .timeout_ticks = cnxk_sso_timeout_ticks, }; static int diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index b8c74633b..a0d76335f 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -18,6 +18,54 @@ cn9k_init_hws_ops(struct cn9k_sso_hws_state *ws, uintptr_t base) ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED; } +static int +cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn9k_sso_hws_dual *dws; + struct cn9k_sso_hws *ws; + int rc; + + if (dev->dual_ws) { + dws = port; + rc = roc_sso_hws_link(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map, + nb_link); + rc |= roc_sso_hws_link(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), + map, nb_link); + } else { + ws = port; + rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link); + } + + return rc; +} + +static int +cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn9k_sso_hws_dual *dws; + struct cn9k_sso_hws *ws; + int rc; + + if (dev->dual_ws) { + dws = port; + rc = roc_sso_hws_unlink(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), + map, nb_link); + rc |= roc_sso_hws_unlink(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), + map, nb_link); + } else { + ws = port; + rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link); + } + + return rc; +} + static void cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) { @@ -54,12 +102,24 @@ cn9k_sso_hws_release(void *arg, void *hws) struct cnxk_sso_evdev *dev = arg; struct cn9k_sso_hws_dual *dws; struct cn9k_sso_hws *ws; + int i; if (dev->dual_ws) { dws = hws; + for (i = 0; i < dev->nb_event_queues; i++) { + roc_sso_hws_unlink(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), + (uint16_t *)&i, 1); + roc_sso_hws_unlink(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), + (uint16_t *)&i, 1); + } memset(dws, 0, sizeof(*dws)); } else { ws = hws; + for (i = 0; i < dev->nb_event_queues; i++) + roc_sso_hws_unlink(&dev->sso, ws->hws_id, + (uint16_t *)&i, 1); memset(ws, 0, sizeof(*ws)); } } @@ -183,6 +243,12 @@ cn9k_sso_dev_configure(const struct rte_eventdev *event_dev) if (rc < 0) goto cnxk_rsrc_fini; + /* Restore any prior port-queue mapping. */ + cnxk_sso_restore_links(event_dev, cn9k_sso_hws_link); + + dev->configured = 1; + rte_mb(); + return 0; cnxk_rsrc_fini: roc_sso_rsrc_fini(&dev->sso); @@ -218,6 +284,38 @@ cn9k_sso_port_release(void *port) rte_free(gws_cookie); } +static int +cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port, + const uint8_t queues[], const uint8_t priorities[], + uint16_t nb_links) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t hwgrp_ids[nb_links]; + uint16_t link; + + RTE_SET_USED(priorities); + for (link = 0; link < nb_links; link++) + hwgrp_ids[link] = queues[link]; + nb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links); + + return (int)nb_links; +} + +static int +cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, + uint8_t queues[], uint16_t nb_unlinks) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t hwgrp_ids[nb_unlinks]; + uint16_t unlink; + + for (unlink = 0; unlink < nb_unlinks; unlink++) + hwgrp_ids[unlink] = queues[unlink]; + nb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks); + + return (int)nb_unlinks; +} + static struct rte_eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, .dev_configure = cn9k_sso_dev_configure, @@ -227,6 +325,9 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = { .port_def_conf = cnxk_sso_port_def_conf, .port_setup = cn9k_sso_port_setup, .port_release = cn9k_sso_port_release, + .port_link = cn9k_sso_port_link, + .port_unlink = cn9k_sso_port_unlink, + .timeout_ticks = cnxk_sso_timeout_ticks, }; static int diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index daf24d84a..e68079997 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -161,6 +161,32 @@ cnxk_setup_event_ports(const struct rte_eventdev *event_dev, return -ENOMEM; } +void +cnxk_sso_restore_links(const struct rte_eventdev *event_dev, + cnxk_sso_link_t link_fn) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t *links_map, hwgrp[CNXK_SSO_MAX_HWGRP]; + int i, j; + + for (i = 0; i < dev->nb_event_ports; i++) { + uint16_t nb_hwgrp = 0; + + links_map = event_dev->data->links_map; + /* Point links_map to this port specific area */ + links_map += (i * RTE_EVENT_MAX_QUEUES_PER_DEV); + + for (j = 0; j < dev->nb_event_queues; j++) { + if (links_map[j] == 0xdead) + continue; + hwgrp[nb_hwgrp] = j; + nb_hwgrp++; + } + + link_fn(dev, event_dev->data->ports[i], hwgrp, nb_hwgrp); + } +} + int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev) { @@ -290,6 +316,16 @@ cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, return 0; } +int +cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns, + uint64_t *tmo_ticks) +{ + RTE_SET_USED(event_dev); + *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz()); + + return 0; +} + static void parse_queue_param(char *value, void *opaque) { diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 79eab1829..97a944d88 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -17,8 +17,9 @@ #define CNXK_SSO_XAE_CNT "xae_cnt" #define CNXK_SSO_GGRP_QOS "qos" -#define NSEC2USEC(__ns) ((__ns) / 1E3) -#define USEC2NSEC(__us) ((__us)*1E3) +#define NSEC2USEC(__ns) ((__ns) / 1E3) +#define USEC2NSEC(__us) ((__us)*1E3) +#define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9) #define CNXK_SSO_MAX_HWGRP (RTE_EVENT_MAX_QUEUES_PER_DEV + 1) #define CNXK_SSO_FC_NAME "cnxk_evdev_xaq_fc" @@ -33,6 +34,8 @@ typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id); typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base); typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws); +typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map, + uint16_t nb_link); struct cnxk_sso_qos { uint16_t queue; @@ -48,6 +51,7 @@ struct cnxk_sso_evdev { uint8_t is_timeout_deq; uint8_t nb_event_queues; uint8_t nb_event_ports; + uint8_t configured; uint32_t deq_tmo_ns; uint32_t min_dequeue_timeout_ns; uint32_t max_dequeue_timeout_ns; @@ -169,6 +173,8 @@ int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev); int cnxk_setup_event_ports(const struct rte_eventdev *event_dev, cnxk_sso_init_hws_mem_t init_hws_mem, cnxk_sso_hws_setup_t hws_setup); +void cnxk_sso_restore_links(const struct rte_eventdev *event_dev, + cnxk_sso_link_t link_fn); void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id, struct rte_event_queue_conf *queue_conf); int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id, @@ -178,5 +184,7 @@ void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, struct rte_event_port_conf *port_conf); int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, cnxk_sso_hws_setup_t hws_setup_fn); +int cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns, + uint64_t *tmo_ticks); #endif /* __CNXK_EVENTDEV_H__ */