From patchwork Fri Apr 30 13:53:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92515 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6F2DFA0546; Fri, 30 Apr 2021 15:54:02 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AF3504069E; Fri, 30 Apr 2021 15:53:56 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A5118410FA for ; Fri, 30 Apr 2021 15:53:52 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13UDoqZA014506; Fri, 30 Apr 2021 06:53:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=8sv1dNR8gC7PEYQsRaI/im8ZYdOgj2kPDe/triv6u4U=; b=Toxig8wVKajNOqFFaUYVhh8BCeLmLNC+zwjXkK+nZT0c30aIXkf7Tt9J9wbNH5AIOrj2 GUrBMldej+7JE01CIniYBc1iTasJ3tDpMm0vgFkJR643dOdTqiF3x4Qky0mSNe/eD7SN 1hIOjmrKvuK01Pfmulv1E1QAJ83wGPUlDVG4ehdQMeUcnxt2ChpLJBeRTg6iTtUZjOcu SlKmtBYKvZ3p3NHY+KaqdYfgjEgxv2iINV7/YClZNTq9owyGaX1pBspFgYGhoXD2cxW2 HWTSGPsULzxXaycmBZHct6rLByJUXE4iPZwzef70L/K4aeTCnsTos4UJCwcp3z8aNR0K Jw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3883jtbfsm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 30 Apr 2021 06:53:51 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 30 Apr 2021 06:53:50 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 30 Apr 2021 06:53:50 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 7404A3F703F; Fri, 30 Apr 2021 06:53:48 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" , Anatoly Burakov CC: Date: Fri, 30 Apr 2021 19:23:06 +0530 Message-ID: <20210430135336.2749-4-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430135336.2749-1-pbhagavatula@marvell.com> References: <20210426174441.2302-1-pbhagavatula@marvell.com> <20210430135336.2749-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: xpB2K7WJqmlM9Sqvmn6WqQSRH9F9T53D X-Proofpoint-ORIG-GUID: xpB2K7WJqmlM9Sqvmn6WqQSRH9F9T53D X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-30_08:2021-04-30, 2021-04-30 signatures=0 Subject: [dpdk-dev] [PATCH v3 03/33] event/cnxk: add platform specific device probe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add platform specific event device probe and remove, also add event device info get function. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cn10k_eventdev.c | 101 +++++++++++++++++++++++++++ drivers/event/cnxk/cn9k_eventdev.c | 102 ++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 2 + drivers/event/cnxk/meson.build | 5 +- 4 files changed, 209 insertions(+), 1 deletion(-) create mode 100644 drivers/event/cnxk/cn10k_eventdev.c create mode 100644 drivers/event/cnxk/cn9k_eventdev.c diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c new file mode 100644 index 000000000..f5caa5537 --- /dev/null +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_eventdev.h" + +static void +cn10k_sso_set_rsrc(void *arg) +{ + struct cnxk_sso_evdev *dev = arg; + + dev->max_event_ports = dev->sso.max_hws; + dev->max_event_queues = + dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ? + RTE_EVENT_MAX_QUEUES_PER_DEV : + dev->sso.max_hwgrp; +} + +static void +cn10k_sso_info_get(struct rte_eventdev *event_dev, + struct rte_event_dev_info *dev_info) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD); + cnxk_sso_info_get(dev, dev_info); +} + +static struct rte_eventdev_ops cn10k_sso_dev_ops = { + .dev_infos_get = cn10k_sso_info_get, +}; + +static int +cn10k_sso_init(struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + int rc; + + if (RTE_CACHE_LINE_SIZE != 64) { + plt_err("Driver not compiled for CN9K"); + return -EFAULT; + } + + rc = plt_init(); + if (rc < 0) { + plt_err("Failed to initialize platform model"); + return rc; + } + + event_dev->dev_ops = &cn10k_sso_dev_ops; + /* For secondary processes, the primary has done all the work */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rc = cnxk_sso_init(event_dev); + if (rc < 0) + return rc; + + cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev)); + if (!dev->max_event_ports || !dev->max_event_queues) { + plt_err("Not enough eventdev resource queues=%d ports=%d", + dev->max_event_queues, dev->max_event_ports); + cnxk_sso_fini(event_dev); + return -ENODEV; + } + + plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d", + event_dev->data->name, dev->max_event_queues, + dev->max_event_ports); + + return 0; +} + +static int +cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) +{ + return rte_event_pmd_pci_probe(pci_drv, pci_dev, + sizeof(struct cnxk_sso_evdev), + cn10k_sso_init); +} + +static const struct rte_pci_id cn10k_pci_sso_map[] = { + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), + { + .vendor_id = 0, + }, +}; + +static struct rte_pci_driver cn10k_pci_sso = { + .id_table = cn10k_pci_sso_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA, + .probe = cn10k_sso_probe, + .remove = cnxk_sso_remove, +}; + +RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso); +RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map); +RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c new file mode 100644 index 000000000..d02c0c9bd --- /dev/null +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_eventdev.h" + +#define CN9K_DUAL_WS_NB_WS 2 +#define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id) + +static void +cn9k_sso_set_rsrc(void *arg) +{ + struct cnxk_sso_evdev *dev = arg; + + if (dev->dual_ws) + dev->max_event_ports = dev->sso.max_hws / CN9K_DUAL_WS_NB_WS; + else + dev->max_event_ports = dev->sso.max_hws; + dev->max_event_queues = + dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ? + RTE_EVENT_MAX_QUEUES_PER_DEV : + dev->sso.max_hwgrp; +} + +static void +cn9k_sso_info_get(struct rte_eventdev *event_dev, + struct rte_event_dev_info *dev_info) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN9K_PMD); + cnxk_sso_info_get(dev, dev_info); +} + +static struct rte_eventdev_ops cn9k_sso_dev_ops = { + .dev_infos_get = cn9k_sso_info_get, +}; + +static int +cn9k_sso_init(struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + int rc; + + if (RTE_CACHE_LINE_SIZE != 128) { + plt_err("Driver not compiled for CN9K"); + return -EFAULT; + } + + rc = plt_init(); + if (rc < 0) { + plt_err("Failed to initialize platform model"); + return rc; + } + + event_dev->dev_ops = &cn9k_sso_dev_ops; + /* For secondary processes, the primary has done all the work */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rc = cnxk_sso_init(event_dev); + if (rc < 0) + return rc; + + cn9k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev)); + if (!dev->max_event_ports || !dev->max_event_queues) { + plt_err("Not enough eventdev resource queues=%d ports=%d", + dev->max_event_queues, dev->max_event_ports); + cnxk_sso_fini(event_dev); + return -ENODEV; + } + + plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d", + event_dev->data->name, dev->max_event_queues, + dev->max_event_ports); + + return 0; +} + +static int +cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) +{ + return rte_event_pmd_pci_probe( + pci_drv, pci_dev, sizeof(struct cnxk_sso_evdev), cn9k_sso_init); +} + +static const struct rte_pci_id cn9k_pci_sso_map[] = { + { + .vendor_id = 0, + }, +}; + +static struct rte_pci_driver cn9k_pci_sso = { + .id_table = cn9k_pci_sso_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA, + .probe = cn9k_sso_probe, + .remove = cnxk_sso_remove, +}; + +RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso); +RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map); +RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 9745bfd3e..6bdf0b347 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -25,6 +25,8 @@ struct cnxk_sso_evdev { uint32_t min_dequeue_timeout_ns; uint32_t max_dequeue_timeout_ns; int32_t max_num_events; + /* CN9K */ + uint8_t dual_ws; } __rte_cache_aligned; static inline struct cnxk_sso_evdev * diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index 88cb472f0..888aeb064 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -8,6 +8,9 @@ if not is_linux or not dpdk_conf.get('RTE_ARCH_64') subdir_done() endif -sources = files('cnxk_eventdev.c') +sources = files('cn10k_eventdev.c', + 'cn9k_eventdev.c', + 'cnxk_eventdev.c', + ) deps += ['bus_pci', 'common_cnxk', 'net_cnxk']