From patchwork Fri Apr 30 13:53:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92533 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 71EEDA0546; Fri, 30 Apr 2021 15:56:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7FBA341335; Fri, 30 Apr 2021 15:54:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9CDEF4133F for ; Fri, 30 Apr 2021 15:54:44 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13UDpJId016402 for ; Fri, 30 Apr 2021 06:54:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=36rTcej0V3XJLHHHHI2nuZBmv9/6pB/Mm4neMLvnb6M=; b=WM6ZPllrRoWFf1zec1yOJVIhOXg/QtBaJLuoG39sQL9BkkRnPLbjtn7EFtmuZgIzBU6t dhXFqKJrvTKxT4WbBvml1vGUP+4S9jfhlRycjwSyiprd2jQqlcMMqfKNx1PqVH5hN3eY a3Ylf+gHgspPxg6X8WDBFdzuYXf5qpUdqnjxkLwey3MY9cxw3H5wOYgXaNhXjX3SJ3g3 F4+GG/Pf8Qwvd8jfyjEfd0fmG8pLB8GbZTwT7I00jvDC4cCWwxyW9b1rcJQ0sY3FA+qF vgW7pxiFblDAs5Yn0ZjGu9rRpJ6g73R2/6NZFhP3o+BItTrUTGbSQPayEIBDddZF9Opa Hg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 387rpneawy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 30 Apr 2021 06:54:43 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 30 Apr 2021 06:54:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 30 Apr 2021 06:54:41 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id EB4843F703F; Fri, 30 Apr 2021 06:54:39 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Fri, 30 Apr 2021 19:23:24 +0530 Message-ID: <20210430135336.2749-22-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430135336.2749-1-pbhagavatula@marvell.com> References: <20210426174441.2302-1-pbhagavatula@marvell.com> <20210430135336.2749-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: -fMwcEHn0gjenyt3-0YySirK-5rHe16U X-Proofpoint-ORIG-GUID: -fMwcEHn0gjenyt3-0YySirK-5rHe16U X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-30_08:2021-04-30, 2021-04-30 signatures=0 Subject: [dpdk-dev] [PATCH v3 21/33] event/cnxk: add timer adapter capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add function to retrieve event timer adapter capabilities. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cn10k_eventdev.c | 2 ++ drivers/event/cnxk/cn9k_eventdev.c | 2 ++ drivers/event/cnxk/cnxk_tim_evdev.c | 22 +++++++++++++++++++++- drivers/event/cnxk/cnxk_tim_evdev.h | 6 +++++- 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 17bed4c9a..c6fde7232 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -420,6 +420,8 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .port_unlink = cn10k_sso_port_unlink, .timeout_ticks = cnxk_sso_timeout_ticks, + .timer_adapter_caps_get = cnxk_tim_caps_get, + .dump = cnxk_sso_dump, .dev_start = cn10k_sso_start, .dev_stop = cn10k_sso_stop, diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index e39d04fdd..4211610c6 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -494,6 +494,8 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = { .port_unlink = cn9k_sso_port_unlink, .timeout_ticks = cnxk_sso_timeout_ticks, + .timer_adapter_caps_get = cnxk_tim_caps_get, + .dump = cnxk_sso_dump, .dev_start = cn9k_sso_start, .dev_stop = cn9k_sso_stop, diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 46461b885..265bee533 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -5,6 +5,26 @@ #include "cnxk_eventdev.h" #include "cnxk_tim_evdev.h" +int +cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, + uint32_t *caps, + const struct rte_event_timer_adapter_ops **ops) +{ + struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); + + RTE_SET_USED(flags); + RTE_SET_USED(ops); + + if (dev == NULL) + return -ENODEV; + + /* Store evdev pointer for later use. */ + dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; + *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; + + return 0; +} + void cnxk_tim_init(struct roc_sso *sso) { @@ -37,7 +57,7 @@ cnxk_tim_init(struct roc_sso *sso) void cnxk_tim_fini(void) { - struct cnxk_tim_evdev *dev = tim_priv_get(); + struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); if (rte_eal_process_type() != RTE_PROC_PRIMARY) return; diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 5ddc94ed4..ece66ab25 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -27,7 +27,7 @@ struct cnxk_tim_evdev { }; static inline struct cnxk_tim_evdev * -tim_priv_get(void) +cnxk_tim_priv_get(void) { const struct rte_memzone *mz; @@ -38,6 +38,10 @@ tim_priv_get(void) return mz->addr; } +int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags, + uint32_t *caps, + const struct rte_event_timer_adapter_ops **ops); + void cnxk_tim_init(struct roc_sso *sso); void cnxk_tim_fini(void);